s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 360

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s908ab32ag0cfue

Manufacturer Part Number
s908ab32ag0cfue
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low-Voltage Inhibit (LVI)
21.4 Functional Description
Technical Data
360
NOTE:
Figure 21-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor
V
generate a reset when V
at or below that level for 9 or more consecutive CPU cycles. Setting the
LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop
mode.
LVISTOP, LVIPWRD, and LVIRSTD are in the configuration register 1
(CONFIG1).
details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
remains in reset until V
the MCU to exit reset.
details of the interaction between the SIM and the LVI. The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
Where LVI trip falling voltage LVI
and LVI trip rising voltage LVI
(See
DD
voltage. The LVI reset bit, LVIRSTD, enables the LVI module to
Section 23. Electrical
DETECTOR
LOW V
V
DD
DD
shows the structure of the LVI module. The LVI is enabled
See Section 6. Configuration Register (CONFIG)
Low-Voltage Inhibit (LVI)
Figure 21-1. LVI Module Block Diagram
V
V
FROM CONFIG1
DD
DD
LVIPWRD
> LVI
≤ LVI
See 8.4.2.5 Low-Voltage Inhibit (LVI) Reset
DD
Trip
Trip
DD
rises above a voltage, LVI
= 0
= 1
falls below a voltage, LVI
Specifications.)
TRIPR
TO LVISR
LVIOUT
TRIPF
= V
STOP INSTRUCTION
FROM CONFIG1
= V
LVII
LVIRSTD
LVII
+ H
LVI
MC68HC908AB32
Freescale Semiconductor
TRIPR
TRIPF
FROM CONFIG1
, which causes
, and remains
LVISTOP
LVI RESET
Rev. 1.1
for
for

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