MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 2

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MT9171AE

Manufacturer Part Number
MT9171AE
Description
Interface, Digital Subscriber Interface Circuit
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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MT9171/72
9-116
Pin Description
4,5,
22
10
11
12
1
2
3
6
7
8
9
CDSTo/CDo
4,5,
CDSTi/CDi
Pin #
24
10
11
12
13
1
2
3
6
7
9
F0/CLD
LOUT
VBias
RegC
VRef
MS2
MS1
MS0
VSS
5,7,
28
10
12
13
14
15
2
3
4
8
9
10
11
1
2
3
4
5
6
7
8
9
MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the
22 PIN PDIP
DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in
F0/CLD
CDSTo/
CDSTi/
RegC
Name
L
V
CDo
V
CDi
V
OUT
Bias
Ref
SS
22
21
20
19
18
17
16
15
14
13
12
Line Out. Transmit Signal output (Analog). Referenced to V
Internal Bias Voltage output. Connect via 0.33 F decoupling capacitor to V
Internal Reference Voltage output. Connect via 0.33 F decoupling capacitor to
V
various operating modes for a particular application. See Table 1 for the
operating modes.
Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative
pulse input for the MASTER indicating the start of the active channel times of the
device. Output for the SLAVE indicating the start of the active channel times of
the device. Output in MOD mode providing a pulse indicating the start of the C-
channel.
Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control
& signalling input in DN mode. In MOD mode this is a continuous bit stream at
the bit rate selected.
Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial
control & signalling output in DN mode. In MOD mode this is a continuous bit
stream at the bit rate selected.
Negative Power Supply (0V).
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
DD
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
CDSTo/CDo
.
CDSTi/CDi
F0/CLD
LOUT
VBias
RegC
VRef
MS2
MS1
MS0
VSS
NC
Figure 2 - Pin Connections
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
24
23
22
21
20
19
18
17
16
15
14
13
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
NC
Description
F0/CLD
RegC
MS2
MS1
MS0
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
Advance Information
Bias
.
25
24
23
22
21
20
19
C4/TCK
NC
LOUT DIS
Precan
OSC1
OSC2
NC
DD
.

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