MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 11

• Manufacturer Part Number: MT9171AE
• Description: Interface, Digital Subscriber Interface Circuit
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
transparently through the DNIC and is transmitted to
or received from the line at the bit rate selected in the
Control Register.
If the bit rate is 80 kbit/s, only D0 is transmitted and
received. At 160 kbit/s, D0 and D1 are transmitted
and received. When the DINB bit is set in the Control
Register the entire D-channel is transmitted and
received in the B1-channel timeslot.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The Control and Diagnostics Registers are
accessed through the C-channel. They contain
information to control the DNIC and carry out the
diagnostics as well as the HK bit to be transmitted on
the line as described in Tables 4 and 5. Bits 0 and 1
of the C-channel select between the Control and
Diagnostics Register. If these bits are 0, 0 then the
C-channel information is written to the Control
Notes:
Bit
0
1
2
3
4
5
6
7
Suggested use of ATTACK:
-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.
-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.
When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
depending upon the status of bit-3.
Reg Sel-1
Reg Sel-1
Reg Sel-2
ATTACK
PSEN
TxHK
DINB
bit 0
Name
DRR
BRS
Reg Sel-2
bit 1
Register Select-1. Must be set to ’0’ to select the Control Register.
Register Select-2. Must be set to ’0’ to select the Control Register.
Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset
to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic
"1", the Diagnostics Register will not be reset.
Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.
D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding
to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit
times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel
timeslot on the line providing a 64 kbit/s D-channel link.
Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and
deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler
are disabled.
Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection
coefficient much faster. Used on power-up for fast convergence. When ’0’, the echo
canceller will require the normal amount of time to converge to a reflection coefficient.
Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as
Housekeeping Bit. When set to ’1’, logic one is transmitted over the line as Housekeeping
Bit.
DRR
bit 2
Table 4. Control Register
bit 3
BRS
DINB
bit 4
Register (Table 4). If they are 0, 1 the C-
written to the Diagnostics Register (Table 5).
The Diagnostics Register Reset bit (bit 2) of the
Control Register determines the reset state of the
Diagnostics Register. If, on writing to the Control
Register, this bit is set to logic “0”, the Diagnostics
Register will be reset coincident with the frame
pulse. When this bit is logic “1”, the Diagnostics
Register will not be reset.
diagnostic features, the Diagnostics Register must
be continuously written to. The output C-channel
sends status information from the Status Register to
the system along with the received HK bit as shown
in Table 6.
In MOD mode, the CD port is no longer an ST-BUS
but is a serial bit stream operating at the bit rate
selected. It continues to transfer the C-channel but
the D-channel and the HK bit no longer exist. DUAL
Default Mode Selection (Refer to Table 4a)
Description
PSEN
bit 5
ATTACK
bit 6
In order to use the
MT9171/72
TxHK
bit 7
c
hannel is
9-125