MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 12

• Manufacturer Part Number: MT9171AE
• Description: Interface, Digital Subscriber Interface Circuit
• Manufacturer: Zarlink Semiconductor, Inc.

MT9171/72
Notes:
Notes:
depending upon the status of bit-3.
port operation must be used in MOD mode. The C-
channel is clocked in and out of the CD port by TCK
and CLD with TCK defining the bits and CLD the
channel boundaries of the data stream as shown in
Figure 8.
Line Port (L
9-126
Bit
2,3
C-Channel
XXX01111
XXX11111
0
1
4
5
6
7
Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.
Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
Do not use L
Do not use DSTo to DSTi loopback in MOD/MAS mode.
(Bit 0-7)
Reg Sel-1
bit 0
IN
Reg Sel-1
Reg Sel-2
Loopback
PSWAP
Not Used
OUT
, L
Name
FUN
DLO
OUT
Internal Control
to L
00000000
00010000
IN
)
Reg Sel-2
Register
loopback in DN/SLV mode.
bit 1
Register Select-1. Must be set to ’0’ to select the Diagnostic Register.
Register Select-2. Must be set to ’1’ to select the Diagnostic Register.
Bit 2
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials are
interchanged (use for MAS mode only). When set to ’0’, the polynomials retain their
normal designations.
Disable Line Out. When set to ’1’, the signal on L
’0’, L
Must be set to ’0’ for normal operation.
0
0
1
1
OUT
bit 2
Bit 3
Internal Diagnostic
0
1
0
1
pin functions normally.
Loopback
Table 4a. Default Mode Selection
01000000
01000000
Register
Table 5. Diagnostic Register
All loopback testing functions disabled. Normal operation.
DSTi internally looped back into DSTo for system diagnostics.
L
DSTo is internally looped back into DSTi for end-to-end testing.
OUT
bit 3
is internally looped back into L
bit 4
FUN
The line interface is made up of L
L
receiving the composite transmit and receive signal
from the line. The line code used in the DNIC is
Biphase and is shown in Figure 10. The scrambled
NRZ data is differentially encoded meaning the
previous differential encoded output is XOR’d with
the current data bit which produces the current
output. This is then biphase encoded where
transitions occur midway through the bit cell with a
Default Mode-1 : Bit rate is 80 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
Default Mode-2 Bit rate is 160 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
OUT
driving the transmit signal onto the line and L
Description
Default Mode Selection
PSWAP
(Refer to Table 4a)
bit 5
OUT
Description
IN
is set set to V
for system diagnostics.
bit 6
DLO
Advance Information
Not Used
Bias
bit 7
OUT
. When set to
and L
IN
with
IN