MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 10

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MT9171AE

Manufacturer Part Number
MT9171AE
Description
Interface, Digital Subscriber Interface Circuit
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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MT9171/72
channel 16 or vice versa. One other feature exists;
ODE, where both the DV and CD ports are tristated
in order that no devices are damaged due to
excessive loading while all DNICs are in a random
state on power up in a daisy chain arrangement.
DV Port (DSTi/Di, DSTo/Do)
The DV port transfers data or PCM encoded voice to
and from the line according to the particular mode
selected by the mode select pins. The modes
affecting the configuration of the DV port are MOD or
DN and DUAL or SINGL. In DN mode the DV port
operates as an ST-BUS at 2.048 Mbit/s with 32, 8 bit
channels per frame as shown in Figure 9. In this
mode the DV port channel configuration depends
upon whether DUAL or SINGL port is selected.
When DUAL port mode is used, the C and D
channels are passed through the CD port and the B1
and B2 channels are passed through the DV port. At
80 kbit/s only one channel of the available 32 at the
DV port is utilized, this being channel 0 which carries
the B1-channel. This is shown in Figure 3. At 160
kbit/s, two channels are used, these being 0 and 16
carrying the B1 and B2 channels, respectively. This
is shown in Figure 4. When SINGL port mode is
used, channels B1, B2, C and D are all passed via
the DV port and the CD port is disabled. See CD port
description for an explanation of the C and D
channels.
The D-channel is always passed during channel time
0 followed by the C and B1 channels in channel
times 1 and 2, respectively for 80 kbit/s. See Figure
5. For 160 kbit/s the B2 channel is added and
occupies channel time 3 of the DV port. See Figure
6. For all of the various configurations the bit orders
are shown by the respective diagram. In MOD mode
the DV and CD ports no longer operate at 2.048
Mbits/s but are continuous serial bit streams
operating at the bit rate selected of 80 or 160 kbit/s.
can be used.
9-124
While in the MOD mode only DUAL port operation
ST-BUS
F0
Channel
31
Channel
0
Channel
1
Significant
Bit (First)
Most
Channel
Figure 9 - ST-BUS Format
2
Bit 7
• • • • • • • •
Bit 6
125 sec
In order for more than one DNIC to be connected to
any one DV and CD port, making more efficient use
of the busses, the DSTo and CDSTo outputs are put
into high impedance during the inactive channel
times of the DNIC. This allows additional DNICs to
be cascaded onto the same DV and CD ports. When
used in this way a signal called F0o is used as an
indication to the next DNIC in a daisy chain that its
channel time is now active. Only the first DNIC in the
chain receives
others receive the F0o from its predecessor in
the chain.
cascaded.
CD Port (CDSTi/CDi, CDSTo/CDo)
The CD port is a serial bidirectional port used only in
DUAL port mode. It is a means by which the DNIC
receives its control information for things such as
setting the bit rate, enabling internal loopback tests,
sending status information back to the system and
transferring low speed signalling data to and from the
line.
The CD port is composed of the C and D-Channels.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The D-channel is used for sending and
receiving signalling information and lower speed
data between the line and the system. In DN/DUAL
mode the DNIC receives a C-channel on CDSTi
while transmitting a C-channel on CDSTo.
channel times later (halfway through the frame) a D-
channel is received on CDSTi while a D-channel is
transmitted on CDSTo. This is shown in Figure 7. The
order of the C and D bytes in DUAL port mode can
be reversed by the mode select pins. See Table 1 for
a listing of the byte orientations.
The D-channel exists only in DN mode and may be
used for transferring low speed data or signalling
information over the line at 8, 16 or 64 kbit/s (by
using the DINB feature). The information passes
Bit 5
Bit 4
3.9 sec
Channel
Bit 3
This allows up to 16 DNICs to be
29
the system frame pulse
Bit 2
Channel
30
Advance Information
Bit 1
Channel
Bit 0
31
Least
Significant
Bit (Last)
Channel
and
0
F
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