MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 18

• Manufacturer Part Number: MT9171AE
• Description: Interface, Digital Subscriber Interface Circuit
• Manufacturer: Zarlink Semiconductor, Inc.

MT9171/72
† Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25 C, for design aid only: not guaranteed and not subject to production testing.
9-132
AC Electrical Characteristics
C4
OSC1
1 TCK/RCK Clock Period
2 TCK/RCK Clock Width
3 TCK/RCK Clock Transition Time
4 CLD to TCK Setup Time
5 CLD to TCK Hold Time
6 CLD Width Low
7 CLD Period
Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
Note 2: At the slave end TCK is phase locked to RCK.
2.0V
0.8V
3.0V
2.0V
RCK
TCK
CLD
C4
F0
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D
and may be skewed with respect to TCK due to end-to-end delay.
The rising edge of TCK will lead the rising edge of RCK by approximately 90
Characteristics
2.0V
0.8V
2.0V
0.8V
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
2.4V
0.4V
2.4V
0.4V
2.4V
0.4V
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
†
- Clock Timing - MOD Mode (Figure 18)
t
t
t
t
Sym
CLDW
CLDS
CLDH
CLDP
t
t
t
CW
CP
t
CT
CLDS
t
F0S
t
CLDW
Min
t
F0W
80 kbit/s
t
CLDH
3.125
3.125
t
8
Typ*
12.5
6.25
6.05
F0H
20
x
t
CP
Max Min
t
CP
t
CP
160 kbit/s
o
J
.
C
t
C4P
3.125
2.925
8
Typ*
6.25
1.56
1.56
20
x
t
CW
t
t
CP
C4W
t
Max
CW
Advance Information
t
C4W
Units
ns
s
s
s
s
s
s
t
CT
o
output
C
t
CT
L
Conditions
=40pF
Test