MT9171AE Zarlink Semiconductor, Inc., MT9171AE Datasheet - Page 13

• Manufacturer Part Number: MT9171AE
• Description: Interface, Digital Subscriber Interface Circuit
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
negative going transition indicating a logic "0" and a
positive going transition indicating a logic "1".
There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
for the line by limiting the spectral content from
0.2f
made available to be put onto the line biased at V
The resulting transmit signal will have a distributed
spectrum with a peak at 3/4f
(L
high or by writing DLO (bit 6) of the Diagnostics
Register to logic “1”. When disabled, L
the V
allow this pin to be left not connected in applications
where this function is not required. The receive
signal is the above transmit signal superimposed on
the signal from the remote end and any reflections or
delayed symbols of the near end signal.
OUT
Register
Baud
Status
Bias
) may be disabled by holding the L
1-2
4-6
0
3
7
to 1.6f
level. L
Baud
SYNC
OUT
CHQual
Rx HK
Future
0
SYNC
Name
and on to a line driver where it is
ID
DIS has an internal pull-down to
Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
Channel Quality - These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
Housekeeping - This bit is the received housekeeping (HK) bit from the far end.
Future Functionality. These bits return Logic 1 when read.
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
1
Baud
CHQual
. The transmit signal
OUT
2
OUT
is forced to
Table 6. Status Register
DIS pin
Rx HK
Bias
3
.
The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.
If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.
4
Future Functionality
Function
5
6
MT9171/72
ID
7
9-127