MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 30

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

9.0
During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90826 is in
the normal functional mode. A 5 K pull-down resistor can be connected to the TRST pin so that the device will
not enter the JTAG test mode during power up.
An external RC network with a time constant of five times the power supply rise time should be connected to the
RESET pin to ensure that the device is properly reset after power up.
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching
matrix. This procedure prevents two serial outputs from driving the same stream simultaneously.
Wait for 600 µs for the APLL module to be stabilized before starting the microprocessor initialization routine.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch. Users can also consider using the memory block programming feature to quickly initialize the
OE, TM0 and TM1 bits in the connection memory. When this process is complete, the microprocessor controlling
the matrices can either bring the ODE pin high or enable the OSB bit in control register to relinquish the high
impedance state control.
10.0
The MT90826 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
10.1
The Test Access Port (TAP) provides access to the many test functions of the MT90826. It consists of three input
pins and one output pin. The following pins are from the TAP.
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Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Resets the JTAG scan structure. This pin is internally pulled to VDD.
Initialization of the MT90826
Test Access Port (TAP)
JTAG Support
Zarlink Semiconductor Inc.
MT90826
30
Data Sheet