MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 13

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

the output data position up to 45ns to compensate for the output delay caused by excessive output loading
conditions. See Figure 7 “Examples for Frame Output Offset Timing”.
The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be
directly written to or read from; data memory locations may be directly read from. A DTA signal is provided to hold
the bus until the asynchronous microport operation is queued into the device.
A13
ODE pin
0
0
0
0
0
0
0
Serial Interface Mode
16 Mbps and 8 Mbps
4 Mbps and 8 Mbps
2 Mbps and 4 Mbps
X
0
1
0
1
A12
0
0
0
0
0
0
0
16 Mbps
8 Mbps
4 Mbps
2 Mbps
A11
OSB bit in Control register
0
0
0
0
0
0
0
A10
0
0
0
0
0
0
0
Table 1 - Stream Usage under Various Operation Modes
A9
0
0
0
0
0
0
0
X
0
0
1
1
Input Stream
A8
Table 3 - Address Map for Registers (A13 = 0)
0
0
0
0
0
0
0
STi15-31
STi12-19
STi16-31
Table 2 - Output High Impedance Control
STi0-31
STi0-15
STi0-15
STi0-31
STi0-15
STi0-31
STi0-11
A7
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
Zarlink Semiconductor Inc.
A5
OE bit in Connection Memory
0
0
0
0
0
0
0
Input Data Rate
MT90826
A4
16 Mbps
16 Mbps
0
0
0
0
0
0
0
8 Mbps
4 Mbps
8 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
13
A3
0
0
0
0
0
0
0
X
0
1
1
1
A2
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
Output Stream
STo16-31
STo12-19
STo16-31
STo0-31
STo0-15
STo0-15
STo0-31
STo0-15
STo0-31
STo0-11
A0
0
1
0
1
0
1
0
Control Register, CR
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
ST-BUS Output Driver
Per Channel High-Z
Output Data Rate
Location
Enable
Enable
Enable
High-Z
16 Mbps
16 Mbps
8 Mbps
4 Mbps
8 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
Data Sheet