MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 19

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

15 - 13
12
11
10
9
8
7
6
5
Bit
BPD2
15
Read/Write Address:
Reset Value:
BPD2-0
Unused
CPLL
CBER
SBER
SFE
Unused
BPE
MBP
BPD1 BPD0
14
Name
13
12
Block Programming Data. These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit is set to 1 and the BPE bit is set to 1, the contents of the
bits BPD2- 0 are loaded into bit 15 to bit 13 of the connection memory. Bit 12 to bit 0 of
the connection memory are set to 0.
Must be zero for normal operation.
PLL Input Frequency Select. When zero or one, the CLK input is 16.384 MHz and
the F0i input is 60 ns wide. When one, the CLK input is 8.192 MHz and the F0i input is
122 ns wide. See Table 6 for the usage of the clock frequency.
Clear Bit Error Rate Register. A zero to one transition in this bit resets the internal
bit error counter and the bit error count register to zero.
Start Bit Error Rate Test. A zero to one transition in this bit starts the bit error rate
test. The bit error test result is kept in the bit error count register. A one to zero
transition stops the bit error rate test and the internal bit error counter.
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the frame alignement (FAR) register changes from
zero to one, the evaluation procedure stops. To start another frame evaluation cycle,
set this bit to zero.
Must be zero for normal operation.
Begin Block programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD2-0 bits have to be defined in
the same write operation. Once the BPE bit is set high, the device requires two frames
to complete the block programming. After the programming function has finished, the
BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the
BPE or MBP can be set to 0 to abort the programming operation.
When BPE = 1, the other bits in the control register must not be changed for two
frames to ensure proper operation.
Memory Block Program. When 1, the connection memory block programming
feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature
is disabled.
0
CPLL
11
0000
0000
CBER
10
Table 5 - Control Register Bits
H
H
,
.
SBER
Zarlink Semiconductor Inc.
9
MT90826
SFE
8
19
0
7
Description
BPE
6
MBP
5
MS
4
OSB
3
DR2
2
DR1
1
Data Sheet
DR0
0