MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 28

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

The correct data memory content will be presented to the data bus (D0-D15) on the second read cycle.
12 - 8
7 - 0
15 - 0
Bit
Bit
BER15
Read/Write Address:
Reset value:
Read Address:
15
15
0
(16.384MHz)
BER14
STo Stream
STo Stream
BSA4 - BSA0
BCA7 - BCA0
14
14
BER15 - BER0
0
Name
Name
CLK
BER13
F0i
13
13
0
BER12
BSA4
Table 12 - Bit Error Input Selection (BISR) Register Bits
12
12
Figure 7 - Examples for Frame Output Offset Timing
Table 13 - Bit Error Count (BECR) Register Bits
BER11
BSA3
11
11
BER Input Stream Address Bits. The number expressed in binary notation on
these bits refers to the input data stream which receives the pseudo random
pattern.
BER Input Channel Address Bits. The number expressed in binary notation
on these bits refers to the input channel which receives the pseudo random
pattern.
Bit Error Rate Count Bits. The number expressed in binary notation on these
bits refers to the bit error counts. The register content can be cleared by
programming the CBER bit in the control register from zero to one.
0011
0000
0012
Bit 7
BER10
H
BSA2
H
H
10
10
for BISR register,
for BECR register,
Bit 7
denotes the starting point of the bit cell
BER9
BSA1
Zarlink Semiconductor Inc.
9
9
MT90826
BER8
BSA0
8
8
28
BCA7
BER7
7
7
BCA6
BER6
6
6
Description
Description
BCA5
BER5
5
5
BCA4
BER4
4
4
BCA3
BER3
3
3
BCA2
BER2
offset=00, (0ns)
offset=01, (-15ns)
2
2
BCA1
BER1
1
1
Data Sheet
BCA0
BER0
0
0