MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 20

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

4
3
2 - 0
Bit
DR2
0
0
0
0
1
1
1
BPD2
15
Read/Write Address:
Reset Value:
MS
OSB
DR2-0
BPD1 BPD0
14
Name
DR1
0
0
1
1
0
0
1
13
Table 6 - Serial Data Rate Selections and External Clock Rates
12
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
For data memory read operations, two consecutive microprocessor cycles are
required. The read address should remain the same for the two consecutive read
cycles. The data memory content from the first read cycle should be ignored. The
correct data memory content will be presented to the data bus on the second read
cycle.
Output Stand By. This bit controls the device output drivers.
Data Rate Select. Input/Output data rate selection. See next table (Table 6) for
detailed programming.
0
DR0
OSB bit ODE pin OE bit
0
1
0
1
0
1
0
0
1
1
0
X
CPLL
11
Table 5 - Control Register Bits (continued)
0000
0000
CBER
Serial Interface Mode
10
H
H
,
.
X
1
0
1
0
16 and 8 Mbps
4 and 8 Mbps
2 and 4 Mbps
SBER
Zarlink Semiconductor Inc.
9
16 Mbps
8 Mbps
4 Mbps
2 Mbps
MT90826
SFE
0
1
1
1
X
8
20
0
STo0 - 31
7
High impedance state
Per-channel high impedance
Enable
Enable
Enable
Description
BPE
6
MBP
16.384 MHz
16.384 MHz
16.384 MHz
(CPLL=0)
5
CLK
MS
4
OSB
3
DR2
2
16.384 MHz
8.192 MHz
8.192 MHz
(CPLL=1)
DR1
1
CLK
Data Sheet
DR0
0