MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 14

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

2.0
A functional Block Diagram of the MT90826 is shown in Figure 1.
2.1
For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and
stored sequentially in the data memory. Depending upon the selected operation programmed in the control register,
the usable data memory may be as large as 4,096 bytes. The sequential addressing of the data memory is
performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries
of the incoming serial data streams.
Data to be output on the serial streams may come from either the data memory or connection memory. Locations in
the connection memory are associated with particular ST-BUS output channels. When a channel is due to be
transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in
connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular
channel on a serial output stream is read from the data memory or connection memory during the previous channel
timeslot. This allows enough time for memory access and parallel-to-serial conversion.
2.2
In the connection mode, the addresses of the input source data for all output channels are stored in the connection
memory. The connection memory is mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 14. Once the
source address bits are programmed by the microprocessor, the contents of the data memory at the selected
address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.
By having several output channels connected to the same input source channel, data can be broadcast from one
input channel to several output channels.
In message mode, the microprocessor writes data to the connection memory locations corresponding to the output
stream and channel number. The lower half (8 least significant bits) of the connection memory content is
A13
0
0
0
0
0
0
0
0
0
0
0
0
Data and Connection Memory
Connection and Message Modes
Functional Description
A12
0
0
0
0
0
0
0
0
0
0
0
0
A11
0
0
0
0
0
0
0
0
0
0
0
0
A10
0
0
0
0
0
0
0
0
0
0
0
0
Table 3 - Address Map for Registers (A13 = 0) (continued)
A9
0
0
0
0
0
0
0
0
0
0
0
0
A8
0
0
0
0
0
0
0
0
0
0
0
0
A7
0
0
0
0
0
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
0
0
0
0
0
Zarlink Semiconductor Inc.
A5
0
0
0
0
0
0
0
0
0
0
0
0
MT90826
A4
0
0
0
0
0
0
0
0
0
1
1
1
14
A3
0
1
1
1
1
1
1
1
1
0
0
0
A2
1
0
0
0
0
1
1
1
1
0
0
0
A1
1
0
0
1
1
0
0
1
1
0
0
1
A0
1
0
1
0
1
0
1
0
1
0
1
0
Input Offset Selection Register 5, DOS5
Input Offset Selection Register 6, DOS6
Input Offset Selection Register 7, DOS7
Frame Output Offset Register, FOR0
Frame Output Offset Register, FOR1
Frame Output Offset Register, FOR2
Frame Output Offset Register, FOR3
Unused
Unused
Unused
Bit Error Input Selection Register, BISR
Bit Error Count Register, BECR
Location
Data Sheet