IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 20

• Manufacturer Part Number: IDT72V845L15PFI
• Description: IC FIFO SYNC 4096X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V845L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V845L15PFI

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. t
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
WCLK
WCLK
RCLK
RCLK
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
WEN
WEN
REN
REN
PAE
PAF
of WCLK and the rising edge of RCLK is less than t
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
the rising edge of WCLK is less than t
SKEW2
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
D-(m+1) Words in FIFO
t
t
CLKH
n words in FIFO
n + 1words in FIFO
CLKH
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
t
ENS
ENS
t
t
SKEW2
t
CLKL
CLKL
(2)
,
(4)
(3)
SKEW2
t
, then the PAF deassertion time may be delayed an extra WCLK cycle.
PAFS
t
t
ENH
ENH
SKEW2
t
PAES
, then the PAE deassertion may be delayed one extra RCLK cycle.
20
n + 1 words in FIFO
n + 2 words in FIFO
D - m Words in FIFO
t
t
ENS
ENS
(2)
(3)
,
t
SKEW2
t
ENH
t
ENH
(3)
COMMERCIAL AND INDUSTRIAL
t
PAES
TEMPERATURE RANGES
t
PAFS
FEBRUARY 11, 2009
n Words in FIFO
n + 1 words in FIFO
D -(m+1) Words
in FIFO
4295 drw 22
4295 drw 23
(2)
,
(3)