IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 14

• Manufacturer Part Number: IDT72V845L15PFI
• Description: IC FIFO SYNC 4096X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V845L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V845L15PFI

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Q
D
NOTES:
1. When t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Q
of RCLK and the rising edge of WCLK is less than t
D
0
0
SKEW1
WCLK
RCLK
Latency Timing apply only at the Empty Boundary (EF = LOW).
- Q
0
0
- D
WEN
WCLK
RCLK
REN
WEN
- Q
- D
REN
OE
EF
OE
17
17
FF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
17
17
SKEW1
t
t
ENS
LOW
DS
LOW
minimum specification, t
DATA IN OUTPUT REGISTER
t
ENS
DATA WRITE 1
t
SKEW1
NO WRITE
t
t
ENH
SKEW1
(1)
DATA IN OUTPUT REGISTER
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
FRL
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
(maximum) = t
t
ENH
t
t
A
FRL
SKEW1
(1)
t
, then FF may not change state until the next WCLK edge.
WFF
CLK
t
REF
+ t
SKEW1
t
DS
. When t
DATA WRITE
SKEW1
14
t
WFF
< minimum specification, t
t
A
t
REF
DATA READ
t
ENS
t
t
ENS
DS
t
SKEW1
FRL
DATA WRITE 2
NO WRITE
(maximum) = either 2 * t
(1)
t
ENH
t
SKEW1
COMMERCIAL AND INDUSTRIAL
DATA READ
t
ENH
t
A
t
TEMPERATURE RANGES
FRL
CLK
t
WFF
(1)
+ t
SKEW1
FEBRUARY 11, 2009
NEXT DATA READ
t
REF
, or t
t
CLK
DS
4295 drw 09
+ t
4295 drw 10
SKEW1
DATA
WRITE
. The