IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 12

• Manufacturer Part Number: IDT72V845L15PFI
• Description: IC FIFO SYNC 4096X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V845L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V845L15PFI

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to V
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
REN, WEN, LD
RCLK, WCLK
FL, RXI, WXI
D
WCLK
0
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
PAF, WXO/
HF, RXO
RCLK
WEN
REN
- D
Q
FF
EF/OR
17
0
FF/IR
- Q
PAE
RS
17
(1)
(2)
Figure 6. Write Cycle Timing with Single Register-Buffered FF FF FF FF FF (IDT Standard Mode)
t
SKEW1
t
CLKH
(1)
t
WFF
t
t
t
t
t
RSF
RSF
RSF
RSF
RSF
t
RS
t
CLK
DATA IN VALID
SKEW1
t
RSS
Figure 5. Reset Timing
CONFIGURATION SETTING
, then FF may not change state until the next WCLK edge.
t
CLKL
t
DS
t
ENS
12
(2)
t
t
DH
ENH
t
t
RSR
RSR
t
WFF
CC
OE = 1
OE = 0
COMMERCIAL AND INDUSTRIAL
or GND).
NO OPERATION
(3)
TEMPERATURE RANGES
IDT Standard Mode
FEBRUARY 11, 2009
FWFT Mode
4295 drw 05
4295 drw 06