IDT72V845L15PFI IDT, Integrated Device Technology Inc, IDT72V845L15PFI Datasheet - Page 23

• Manufacturer Part Number: IDT72V845L15PFI
• Description: IC FIFO SYNC 4096X18 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V845L15PFI

• Function: Asynchronous, Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 60mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V845L15PFI

OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
72V825/72V835/72V845 may be used as a stand-alone device when the
WIDTH EXPANSION CONFIGURATION
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
NOTE:
1. Do not connect any output control signals directly together.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Each of the two FIFOs contained in a single IDT72V805/72V815/
Word width may be increased simply by connecting together the control
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
DATA IN (D)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
Figure 29. Block Diagram of the Two FIFOs Contained in One IDT72V805/72V815/72V825/72V835/72V845
FULL FLAG/INPUT
READY (FF/IR)
0
- D
36
17
(one of the two FIFOs contained in the IDT72V805/72V815/72V825/72V835/72V845)
)
18
FF/IR
FL
RESET (RS)
FIFO A
WXI RXI
Configured for a 36-Bit Width Expansion
EF/OR
FL
18
72V805
72V815
72V825
72V835
72V845
23
IDT
RXI
18
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two
IDT72V805/72V815/72V825/72V835/72V845s. Any word width can be
attained by adding additional IDT72V805/72V815/72V825/72V835/72V845s.
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 29). Please see the Application Note AN-83.
application requirements are for 256/512/1,024/2,048/4,096 words or less.
These FIFOs are in a single Device Configuration when the First Load (FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
RESET (RS)
WXI
FF/IR
FL
RESET (RS)
FIFO B
WXI RXI
EF/OR
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
DATA OUT (Q
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
18
EMPTY FLAG/OUTPUT
READY (EF/OR)
OUTPUT ENABLE (OE)
READ CLOCK (RCLK)
READ ENABLE (REN)
PROGRAMMABLE (PAF)
0
COMMERCIAL AND INDUSTRIAL
- Q
DATA OUT (Q)
17
)
TEMPERATURE RANGES
FEBRUARY 11, 2009
4295 drw 29
36
4295 drw 28