EM639165 Etron Technology Inc., EM639165 Datasheet - Page 17

• Manufacturer Part Number: EM639165
• Description: 8Mega x 16bits SDRAM
• Manufacturer: Etron Technology Inc.

Preliminary
WRITE
After tRCD from the bank activation, a WRITE command
can be issued. 1st input data is set at the same cycle as the
WRITE. Following (BL -1) data are written into the RAM,
when the Burst Length is BL. The start address is specified
by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address
sequence of burst data is defined by the Burst Type. A
WRITE command may be applied to any active bank, so
the row precharge time (tRP) can be hidden behind con-
tinuous input data by interleaving the multiple banks. From
Command
Command
BA0,1
BA0,1
A0-9
CLK
A0-9
A10
A11
CLK
A10
A11
DQ
DQ
ACT
ACT
Xa
Xa
Xa
Xa
Xa
00
Xa
Xa
Xa
00
Multi Bank Interleaving WRITE (BL=4)
WRITE with Auto-Precharge (BL=4)
tRCD
tRCD
Write
Write
Da0
Da0
00
00
Y
0
Y
1
ACT
Da1
17
Da1
Xb
Xb
Xb
10
Da2
Da2
the last input data to the PRE command, the write recovery
time (tWR) is required. When A10 is high at a WRITE
command, the autoprecharge (WRITEA) is performed. Any
command (READ, WRITE, PRE, TBST, ACT) to the same
bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data
cycle. (Need to keep tRAS min.) The next ACT command
can be issued after tRP from the internal precharge timing.
tRCD
Da3
Da3
0
Internal precharge starts
Write
Db0
tWR
10
Y
PRE
Db1
00
0
0
Db2
tRP
ACT
Db3
Rev 1.0
Xa
Xa
Xa
00
EM639165
PRE
10
0
0
Feb. 2001