EM636165TS-6G Etron Technology Inc., EM636165TS-6G Datasheet
EM636165TS-6G
Manufacturer Part Number
EM636165TS-6G
Description
Manufacturer
Etron Technology Inc.
Datasheet
1.EM636165TS-6G.pdf
(60 pages)
Specifications of EM636165TS-6G
Case
SSOP-50
Date_code
04+
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Features
• Fast access time: 5/5/5.5/5.5 ns
• Fast clock rate: 183/166/143 MHz
• Self refresh mode: standard and low power
• Internal pipelined architecture
• 512K word x 16-bit x 2-bank
• Programmable Mode registers
• Individual byte controlled by LDQM and UDQM
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• JEDEC standard +3.3V ± 0.3V power supply
• Interface: LVTTL
• 50-pin 400 mil plastic TSOP II package
• 60-ball, 6.4x10.1mm VFBGA package
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
- Pb free and Halogen free
- Pb free
Etron Confidential
Key Specifications
Ordering Information
TS : indicates TSOP II package
VE : indicates VFBGA package
L: indicates Low Power
G: indicates Pb and Halogen Free for TSOPII Package
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
t
t
t
EM636165TS/VE-55G
EM636165TS/VE-6G
EM636165TS/VE-7G
EM636165TS/VE-7LG
t
RAS Row Active time(max.)
CK3 Clock Cycle time(min.)
AC3 Access time from CLK(max.)
RC
i
ndicates Pb Free for VFBGA Package
Part Number
Row Cycle time(min.)
EM636165
FAX: (886)-3-5778671
Frequency
183MHz
166MHz
143MHz
143MHz
1M x 16 bit Synchronous DRAM (SDRAM)
Overview
synchronous DRAM containing 16 Mbits. It is internally
configured as a dual 512K word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 16 bit banks is organized as 2048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications
TSOP II, VFBGA
TSOP II, VFBGA
TSOP II, VFBGA
TSOP II, VFBGA
The EM636165 SDRAM is a high-speed CMOS
The EM636165 provides for programmable Read or
38.5/42/49/49 ns
56.5/60/70/70 ns
5/5/5.5/5.5
Package
-55/6/7/7L
5.5/6/7/7
ns
ns
(Rev.3.4, Apr./2008)
EM636165
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