EM639165 Etron Technology Inc., EM639165 Datasheet - Page 13

• Manufacturer Part Number: EM639165
• Description: 8Mega x 16bits SDRAM
• Manufacturer: Etron Technology Inc.

Preliminary
POWER ON SEQUENCE
Before starting normal operation, the following power on
sequence is necessary to prevent a SDRAM from damaged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
2. Maintain stable power, stable clock, and NOP input con-
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or
5. Issue a mode register set command to initialize the mode
After these sequence, the SDRAM is idle state and ready
for normal operation.
LATENCY
high, DQM high and NOP condition at the inputs.
ditions for a minimum of 200µs.
more auto-refresh commands.
register.
MODE
BA0
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BA1
CL
0
A1 1 A1 0 A9
FP: Full Page
R: Reserved for Future Use
0
/CAS LATENCY
0
0
R
R
R
R
R
R
2
3
A8
0
A7
0
A6
LTMODE
A5
13
A4 A3
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be pro-
grammed by setting the mode register (MRS). The mode
register stores these data until the next MRS command,
which may be issued when all banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for new
command.
BT
LENGTH
BURST
BURST
TYPE
A2
BL
A1
BA0,1 A11-A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
A0
1
0
CLK
/CS
/RAS
/CAS
/WE
SEQUENTIAL
INTERLEAVED
BT= 0
FP
1
2
4
8
R
R
R
Rev 1.0
V
BT= 1
EM639165
1
2
4
8
R
R
R
R
Feb. 2001