EM639165 Etron Technology Inc., EM639165 Datasheet
EM639165
Available stocks
Related parts for EM639165
EM639165 Summary of contents
Page 1
... RAS t Row Cycle time(min.) RC Overview EM639165 is a high-speed Synchronous Dynamic Random Access Memory (SDRAM), organized as 4 banks x 2,097,152 words x 16 bits. All inputs and outputs are referenced to the rising edge of CLK. It achieves very high-speed data rates up to 133MHz, and is suitable for main memories or graphic memories in computer systems ...
Page 2
... Preliminary DQ0-15 I/O Buffer Memory Array Memory Array 4096 x512x16 4096 x512x16 Cell Array Cell Array Bank #1 Bank #2 Control Circuitry Control Signal Buffer Clock Buffer /CS /RAS CLK CKE 2 EM639165 Memory Array 4096 x512x16 Cell Array Bank #3 /WE /CAS DQM Rev 1.0 Feb. 2001 ...
Page 3
... When DQM(U/L) is high in burst write, Din for the current cycle is masked. When DQM(U/L) is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VDDQ and VSSQ are supplied to the Output Buffers only. 3 EM639165 Rev 1.0 Feb. 2001 ...
Page 4
... BASIC FUNCTIONS The EM639165 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS CLK /CS /RAS /CAS /WE CKE A10 Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA ...
Page 5
... WRITE READ READA REFA REFS REFSX TBST MRS 5 EM639165 /WE BA0 ...
Page 6
... BA, RA ACT PRE / L BA, A10 PREA REFA Op-Code MRS Mode-Add 6 EM639165 NOP NOP ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 ...
Page 7
... Terminate Burst, Latch CA,Begin H BA, CA, A10 READA Read, Determine Auto-Precharge*3 WRITE / Terminate Burst, Latch CA,Begin L BA, CA, A10 WRITEA Write, Determine Auto-Precharge*3 H BA, RA ACT Bank Active / ILLEGAL*2 PRE / L BA, A10 Terminate Burst, Precharge PREA H X REFA ILLEGAL Op-Code, L MRS ILLEGAL Mode-Add 7 EM639165 Rev 1.0 Feb. 2001 ...
Page 8
... ACT PRE / L BA, A10 PREA REFA Op-Code MRS Mode-Add 8 EM639165 Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL ...
Page 9
... PRE / L BA, A10 PREA REFA Op-Code MRS Mode-Add 9 EM639165 Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2 ILLEGAL*2 ...
Page 10
... WRITE H H BA, RA ACT PRE / H L BA, A10 PREA REFA Op-Code MRS Mode-Add 10 EM639165 Action NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Rev 1.0 Feb. 2001 ...
Page 11
... H X NOP TBST READ / L X BA, CA, A10 WRITE H H BA, RA ACT PRE / H L BA, A10 PREA REFA Op-Code MRS Mode-Add 11 EM639165 Action NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Rev 1.0 Feb. 2001 ...
Page 12
... EM639165 Action INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh ...
Page 13
... MRS command, the SDRAM is ready for new command LTMODE BT BURST R LENGTH BURST R TYPE 13 EM639165 CLK /CS /RAS /CAS /WE BA0,1 A11- BT ...
Page 14
... EM639165 Write Burst Length Burst Type Interleaved ...
Page 15
... The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA. tRCmin ACT READ PRE tRAS Qa0 Precharge all 15 EM639165 ACT tRP Qa1 Qa2 Qa3 Rev 1.0 Feb. 2001 ...
Page 16
... Qa0 /CAS latency BL + tRP READ tRCD Qa0 Internal precharge start READ BL Qa0 Qa0 Qa1 Internal Precharge Start Timing 16 EM639165 READ PRE Qa1 Qa2 Qa3 Qb0 Qb1 Burst Length ACT tRP Qa1 Qa2 Qa3 ...
Page 17
... WRITE with Auto-Precharge (BL=4) Write ACT tRCD tRCD Da0 Da1 Da2 Da3 Write tRCD Da0 Da1 Da2 Da3 17 EM639165 Write PRE PRE Db0 Db1 Db2 Db3 ACT tRP tWR Internal precharge starts Rev 1.0 ...
Page 18
... READ Command Y i A0-9 0 A10 A11 00 BA0,1 DQM Q D Preliminary READ READ Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Write Qai0 Daj0 Daj1 Daj2 DQM control Write control 18 EM639165 Qal0 Qal1 Qal2 Qal3 Daj3 Rev 1.0 Feb. 2001 ...
Page 19
... Command CL=2 DQ Command DQ Preliminary Latency result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. PRE READ Q0 Q1 READ PRE Q0 Q1 READ PRE Q0 READ PRE READ PRE Q0 Q1 READ PRE Q0 19 EM639165 Q2 Rev 1.0 Feb. 2001 ...
Page 20
... Command CL=3 DQ Command DQ Command DQ Command CL=2 DQ Command DQ Preliminary READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. TBST READ Q0 Q1 READ TBST Q0 Q1 READ TBST Q0 READ TBST READ TBST Q0 Q1 READ TBST Q0 20 EM639165 Q2 Rev 1.0 Feb. 2001 ...
Page 21
... Write READ A0 A10 A11 BA0 DQM DQ Dai0 Preliminary Write Write Daj1 Dbk0 Dbk1 Dbk2 Dal0 Qaj0 Qaj1 21 EM639165 Dal1 Dal2 Dal3 Write READ Dbk0 Dbk1 Rev 1.0 Qal0 Feb. 2001 ...
Page 22
... WRITE to TBST interval is minimum 1 CLK. CLK Command ACT A0-9,11 Xa A10 0 BA0 Preliminary Write PRE tWR Write Interrupted by Terminate (BL=4) Write TBST EM639165 ACT tRP Write Rev 1.0 Feb. 2001 ...
Page 23
... CLK Command Write A0-9,11 Ya A10 1 BA0 auto-precharge Preliminary Write BL Yb tWR interrupted Read BL Yb tWR Qb0 Qb1 interrupted 23 EM639165 ACT tRP activate ACT tRP Qb2 Qb3 activate Rev 1.0 Feb. 2001 ...
Page 24
... Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal. [Single Write] When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0). Preliminary Read BL tRP Qa0 Qa1 Qb0 Qb1 interrupted activate 24 EM639165 ACT Qb2 Qb3 Rev 1.0 Feb. 2001 ...
Page 25
... Auto Refresh on All Banks Preliminary banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be sup- plied to the device before tRC from the REFA command. Auto-Refresh NOP or DESELECT minimum tRFC Auto Refresh on All Banks 25 EM639165 Rev 1.0 Feb. 2001 ...
Page 26
... CKE=H. After tRC from the 1st CLK egde following CKE=H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh Stable CLK Self Refresh Exit 26 EM639165 NOP new command X 00 minimum tRFC for recovery Rev 1 ...
Page 27
... A command at the suspended cycle is ignored. tIH tIS tIH tIS Power Down by CKE Standby Power Down NOP NOP Active Power Down NOP NOP DQ Suspend by CKE (CL=2) Read EM639165 Rev 1.0 Feb. 2001 ...
Page 28
... During writes, DQM(U,L) masks input data word by word. DQM(U,L) to write mask latency CLK Command Write DQM D0 DQ masked by DQM(U,L)=H Preliminary is 0. During reads, DQM(U,L) forces output to Hi-Z word by word. DQM(U,L) to output Hi-Z latency is 2. DQM Function(CL=3) READ EM639165 disabled by DQM(U,L)=H Rev 1.0 Feb. 2001 ...
Page 29
... Input Capacitance, I/O pin Preliminary Condition with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ Ta = 25˚C Parameter Min. 3.0 3.0 2.0 -0.3 Test Condition @ 1MHz 1.4V bias 200mV swing Vcc=3.3V 29 EM639165 Rating Unit V -0.5 - 4.6 V -0.5 - 4.6 V -0.5 - 4.6 V -0 1000 ˚ ˚C -65 - 150 Typ. Max. ...
Page 30
... CKE=VIHmin Icc3NS tCLK=VILmax(fixed) All Bank Active Icc4 tCLK = min BL=4, CL=3, IOL=0mA Icc5 tRC=min, tCLK=min Standard Icc6 CKE < 0.2V Low-Power Test Conditions IOH=-2mA IOL= 2mA Q floating VO VDDQ VIH = 0 -- VDDQ +0.3V 30 EM639165 Max. -75 -8 100 95 110 100 130 120 ...
Page 31
... Refresh Interval time CLK DQ Preliminary -75 Min. 10 CL=2 CL=3 7.5 2.5 2.5 1 1.8 (all inputs) 1 (all inputs) 67 1.4V 1.4V 31 EM639165 -8 Max. Max. Min 100K 100K Any AC timing is referenced to the input signal passing through 1.4V. Rev 1.0 ...
Page 32
... If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter. Output Load Condition V OUT 50pF CLK DQ Preliminary -75 Max. Min. CL=2 6 CL=3 5.4 CL 5.4 CLK DQ Output Timing Measurement Reference Point tOLZ tOHZ tAC tOH 32 EM639165 -8 Unit Max. Min 1.4V 1.4V 1.4V 1.4V Rev 1.0 Note *1 Feb. 2001 ...
Page 33
... CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE#0 Preliminary tRC tRAS tRP tWR PRE#0 ACT # 0 33 EM639165 tRCD tWR WRITE#0 Rev 1 PRE#0 Feb. 2001 ...
Page 34
... Preliminary tRC tRC tRAS tRP tRCD tWR PRE#0 ACT# 0 ACT#1 WRITEA#1 (Auto-Precharge) 34 EM639165 tRCD tWR WRITE#0 ACT#1 Rev 1 PRE#0 Feb. 2001 ...
Page 35
... CKE DQM A0 A10 X A9,11 X BA0 ACT#0 READ# 0 Preliminary tRC tRP tRCD PRE#0 ACT# 0 READ EM639165 tRAS PRE#0 Rev 1.0 Feb. 2001 ...
Page 36
... BA0 ACT#0 READA# 0 Preliminary tRC tRC tRCD ACT# 0 ACT#1 READA EM639165 tRAS tRCD READ# 0 PRE#0 ACT# 1 Rev 1 Feb. 2001 ...
Page 37
... ACT#0 WRITE# 0 ACT#1 Preliminary WRITE# 0 WRITEA# 1 interrupt interrupt same other bank bank 37 EM639165 tWR WRITE# 0 PRE#0 interrupt other bank Rev 1 ACT# 1 Feb. 2001 ...
Page 38
... DQ ACT#0 READ#0 ACT#1 Preliminary tRCD READ#1 READA# 1 interrupt interrupt other same bank bank 38 EM639165 READ# 0 interrupt ACT# 1 other bank Rev 1.0 16 Feb. 2001 ...
Page 39
... Write Interrupted by Read, Read Interrupted by Write @BL=4,CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 WRITE# 0 ACT#1 Preliminary tRCD READ#1 39 EM639165 tWR WRITE# 1 PRE#1 Rev 1.0 16 Feb. 2001 ...
Page 40
... CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE# 0 Preliminary tRP tRCD tWR ACT#0 PRE#0 Te rminate 40 EM639165 tRC tRAS tRP READ# 0 PRE#0 ACT#0 Te rminate Rev 1.0 16 Feb. 2001 ...
Page 41
... Write/Read Terminated by Burst Terminate @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE# 0 Preliminary READ# 0 TERM TERM 41 EM639165 tWR WRITE#0 Rev 1 PRE#0 Feb. 2001 ...
Page 42
... Single Write Burst Read @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE# 0 READ# 0 Preliminary EM639165 Rev 1.0 16 Feb. 2001 ...
Page 43
... Power-Up Sequesce and Intialize CLK 200µs /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ NOP Power On PRE ALL REFA Preliminary tRP tRFC REFA Minimum 8 REFA cycles 43 EM639165 tRFC tRSC REFA MRS ACT# 0 Rev 1.0 Feb. 2001 ...
Page 44
... Auto Refresh CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL REFA All bank s m ust be idle before REFA is issued. Preliminary tRFC ACT#0 44 EM639165 tRCD WRITE#0 Rev 1.0 16 Feb. 2001 ...
Page 45
... CLK /CS tRP /RAS /CAS /WE CKE DQM A0-8, A10 A9,11 BA0,1 DQ PRE ALL Self Refres h Entry All bank s m ust be idle before REFS is issued. Preliminary EM639165 tRFC Self Refres h Exit ACT#0 Rev 1 Feb. 2001 ...
Page 46
... CLK Suspension @BL=4,CL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0 A10 X A9,11 X BA0 ACT#0 WRITE# 0 Preliminary internal READ# 0 CLK suspended 46 EM639165 internal CLK suspended Rev 1.0 Feb. 2001 ...
Page 47
... Power Down CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ PRE ALL Preliminary Standby Power Down ACT EM639165 Active Power Down Rev 1.0 Feb. 2001 ...
Page 48
... EM639165 Normal Max 1.194 - 0.1 0.150 1.044 - 0.35 0.40 1.165 0.210 22.238 22.327 10.16 10.262 0.80 - 11.8365 11.938 0.50 0.597 0. Rev 1 Feb. 2001 ...