EM639165 Etron Technology Inc., EM639165 Datasheet - Page 15

• Manufacturer Part Number: EM639165
• Description: 8Mega x 16bits SDRAM
• Manufacturer: Etron Technology Inc.

Bank Activation and Precharge All (BL=4, CL=3)
Preliminary
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by
the ACT command with the bank addresses (BA0,1). A row is indi-
cated by the row addresses A0-11. The minimum activation interval
between one bank and the other bank is tRRD. Maximum 2 ACT
commands are allowed within tRC , although the number of banks
which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When
multiple banks are active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank
can be issued.
Command
BA0,1
A0-9
CLK
A10
A11
DQ
2 ACT command / tRCmin
ACT
Xa
Xa
Xa
00
tRRD
tRCD
ACT
Xb
Xb
Xb
01
READ
Y
0
00
tRCmin
15
tRAS
READ
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the /CAS Latency from the
READ, followed by (BL -1) consecutive data when the Burst Length
is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8),
A0-8(X16) , and the address sequence of burst data is defined by
the Burst Type. A READ command may be applied to any active
bank, so the row precharge time (tRP) can be hidden behind
continuous output data by interleaving the multiple banks. When
A10 is high at a READ command, the auto-precharge (READA) is
performed. Any command (READ, WRITE, PRE, TBST, ACT) to
the same bank is inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA. (Need to keep
tRAS min.) The next ACT command can be issued after (BL +
tRP) from the previous READA.
Qa0
Precharge all
PRE
Qa1
1
Qa2
tRP
Qa3
ACT
Xb
Xb
Xb
01
Rev 1.0
EM639165
Feb. 2001