74HC40105N,652 NXP Semiconductors, 74HC40105N,652 Datasheet - Page 17

• Manufacturer Part Number: 74HC40105N,652
• Description: IC FIFO REGISTER 4X16 16DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC40105N,652

• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 2 V ~ 6 V
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Family: HC
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• High Level Output Current: -7.8mA
• Low Level Output Current: 7.8mA
• Propagation Delay Time: 750ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Through Hole
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 8uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HC40105N; 74HC40105N; 933669660652

Philips Semiconductors
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFO
generated. The requirements of SI
edge of DOR
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
full. After a bubble-up delay a DIR
from the output of FIFO
width of DOR
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
1998 Jan 23
4-bit x 16-word FIFO register
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFO
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
A
B
. After a second bubble-up delay an empty space arrives at D
and Q
nA
. After a second ripple through delay, data arrives at the output of FIFO
A
to the input of FIFO
Fig.19 Cascading for increased word capacity; 32 words
R
B
pulse is generated, which acts as a SO
and D
nB
B
are satisfied by the DOR
. The requirements of the SO
17
A
4 bits
A
pulse width and the timing between the rising
. Due to SO
A
A
nA
pulse for FIFO
pulse for FIFO
, at which time DIR
R
pulse, when both FIFOs are initially
A
being HIGH, a DOR pulse is
4 bits.
74HC/HCT40105
A
A
A
. One word is transferred
and FIFO
is satisfied by the pulse
B
.
A
Product specification
goes HIGH.
B
. Fig.22 gives an