74HC40105N,652 NXP Semiconductors, 74HC40105N,652 Datasheet - Page 13

• Manufacturer Part Number: 74HC40105N,652
• Description: IC FIFO REGISTER 4X16 16DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC40105N,652

• Function: Asynchronous
• Memory Size: 64 (4 x 16)
• Data Rate: 25MHz
• Voltage - Supply: 2 V ~ 6 V
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Logic Family: HC
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• High Level Output Current: -7.8mA
• Low Level Output Current: 7.8mA
• Propagation Delay Time: 750ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 36(Typ)MHz
• Mounting: Through Hole
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 8uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HC40105N; 74HC40105N; 933669660652

Philips Semiconductors
With FIFO empty; SO is held HIGH in anticipation
agewidth
Shift-in operation; high-speed burst mode
1998 Jan 23
4-bit x 16-word FIFO register
(1) HC : V
Fig.10 Waveforms showing ripple through delay SI input to DOR output
(1) HC : V
Fig.11 Waveforms showing SI minimum pulse width and SI maximum
HCT : V
HCT : V
SO INPUT
DOR OUTPUT
Q OUTPUT
SI INPUT
n
and propagation delay from the DOR pulse to the Q
pulse frequency, in high-speed shift-in burst mode.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
1
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
V M
(1)
2
CC
CC
V M
.
.
(1)
ripple through
t PLH
delay
4
3
V M
(1)
t PHL / t PLH
5
13
t PHL
6
n
MBA337
output.
Notes to Fig.10
1. FIFO is initially empty, SO is held
2. SI pulse; loads data into FIFO
3. DOR flag signals the arrival of
4. Output transition; data arrives at
5. SO set LOW; necessary to
6. DOR goes LOW; FIFO is empty
Note to Fig.11
In the high-speed mode, the burst-in
rate is determined by the minimum
shift-in HIGH and shift-in LOW
specifications. The DIR status flag is
a don’t care condition, and a shift-in
pulse can be applied regardless of the
flag. A SI pulse which would overflow
the storage capacity of the FIFO is
ignored.
HIGH.
and initiates ripple through
process.
valid data at the output stage.
output stage after the specified
propagation delay between the
rising edge of the DOR pulse to
the Q
complete shift-out process. DOR
remains LOW, because FIFO is
empty.
again.
74HC/HCT40105
n
output.
Product specification