SCANSTA111 National Semiconductor Corporation, SCANSTA111 Datasheet - Page 5

• Manufacturer Part Number: SCANSTA111
• Description: Enhanced Scan Bridge Multidrop Addressable Ieee 1149.1 Jtag Port
• Manufacturer: National Semiconductor Corporation

TRST
A
Y
LSP_ACTIVE
TRIST
TEST ENABLE
(0-1)
(0-1)
Note 1: Refer to the IBIS model on our website for I/O characteristics.
Application Overview
ADDRESSING SCHEME - The SCANSTA111 architecture
extends the functionality of the IEEE 1149.1 Standard by
supplementing that protocol with an addressing scheme
which allows a test controller to communicate with specific
’STA111s within a network of ’STA111s. That network can
include both multi-drop and hierarchical connectivity. In ef-
fect, the ’STA111 architecture allows a test controller to
dynamically select specific portions of such a network for
participation in scan operations. This allows a complex sys-
tem to be partitioned into smaller blocks for testing purposes.
The ’STA111 provides two levels of test-network partitioning
capability. First, a test controller can select individual
’STA111s, specific sets of ’STA111s (multi-cast groups), or all
’STA111s (broadcast). This ’STA111-selection process is
supported by a Level-1 communication protocol. Second,
within each selected ’STA111, a test controller can select
one or more of the chip’s three local scan-ports. That is,
individual local ports can be selected for inclusion in the
(single) scan-chain which a ’STA111 presents to the test
controller. This mechanism allows a controller to select spe-
cific terminal scan-chains within the overall scan network.
The port-selection process is supported by a Level-2 proto-
col.
HIERARCHICAL SUPPORT - Multiple SCANSTA111’s can
be used to assemble a hierarchical boundary-scan tree. In
such a configuration, the system tester can configure the
local ports of a set of ’STA111s so as to connect a specific
set of local scan-chains to the active scan chain. Using this
capability, the tester can selectively communicate with spe-
cific portions of a target system. The tester’s scan port is
Pin Name
(0-2)
(0-2)
(0-2)
Pins
No.
3
2
2
3
3
1
I/O
O
O
O
O
I
I
LOCAL TEST RESETS: A gated version of TRST
current.
LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the
backplane pin Y
These inputs have an internal pull-up resistor.
LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the
backplane pin A
These outputs have 24mA of drive current.
LOCAL ANALOG TEST BUS ENABLE: These analog pins serve as enable signals for analog
busses supporting the IEEE 1149.4 Mixed-Signal Test Bus standard , or for backplane
physical layer changes (i.e.; TTL to LVDS). These outputs have 12mA of drive current.
LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports
are TRI-STATEd . These pins are used for backplane physical layer changes (i.e.; TTL to
LVDS). These outputs have 12mA of drive current.
TEST ENABLE INPUT: This pin is used for factory test and should be tied to V
operation.
TABLE 2. Pin Descriptions (Continued)
B
B
. (Only on LSP
. (Only on LSP
5
connected to the backplane scan port of a root layer of
’STA111s, each of which can be selected using multi-drop
addressing. A second tier of ’STA111s can be connected to
this root layer, by connecting a local port (LSP) of a root-
layer ’STA111 to the backplane port of a second-tier
’STA111. This process can be continued to construct a multi-
level scan hierarchy. ’STA111 local ports which are not cas-
caded into higher-level ’STA111s can be thought of as the
terminal leaves of a scan tree. The test master can select
one or more target leaves by selecting and configuring the
local ports of an appropriate set of ’STA111s in the test tree.
Check with your ATPG tool vendor to ensure support of this
feature.
State Machines
The ’STA111 is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a scan tester can select indi-
vidual ’STA111s for participation in upcoming scan opera-
tions. STA111 selection is accomplished by simultaneously
scanning a device address out to multiple STA111s. Through
an on-chip address matching process, only those ’STA111s
whose statically-assigned address matches the scanned-out
address become selected to receive further instructions from
the scan tester. STA111 selection is done using a Level-1
protocol, while follow-on instructions are sent to selected
’STA111s by using a Level-2 protocol.
0
0
and LSP
and LSP
Description
1
1
. Only available when a single LSP is selected) .
. Only available when a single LSP is selected) .
B
. These outputs have 24mA of drive
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