SCANSTA111 National Semiconductor Corporation, SCANSTA111 Datasheet - Page 18

• Manufacturer Part Number: SCANSTA111
• Description: Enhanced Scan Bridge Multidrop Addressable Ieee 1149.1 Jtag Port
• Manufacturer: National Semiconductor Corporation

www.national.com
Register Descriptions
count (zero). It is cleared (logic 0) when the counter is loaded
following a CNTRSEL instruction. The power-on value for bit
7 is 0.
DEVICE IDENTIFICATION REGISTER: The device identifi-
cation register (IDREG) is a 32-bit register compliant with
IEEE Std. 1149.1. When the IDCODE instruction is active,
the identification register is loaded with the Hex value upon
leaving the Capture-DR state (on the rising edge of the
TCK
website for the most accurate Device ID.
LINEAR FEEDBACK SHIFT REGISTER: The ’STA111 con-
tains a signature compactor which supports test result evalu-
ation in a multi-chain environment. The signature compactor
consists of a 16-bit linear-feedback shift register (LFSR)
which can monitor local-port scan data as it is shifted up-
stream from the ’STA111’s local-port network. Once the
LFSR is enabled, the LFSR’s state changes in a reproduc-
ible way as each local-port data bit is shifted in from the
local-port network. When all local-port data has been
scanned in, the LFSR contains a 16-bit signature value
which can be compared against a signature computed for
the expected results vector.
The LFSR uses the following feedback polynomial:
BIT
Description
Used in Silicon Y
Default Value
BIT
Description
Used in Silicon N
Default Value
BIT
Description
Used in Silicon
Default Value
BIT
Description
Used in Silicon
Default Value
BIT
Description
B
). Refer to the currently available BSDL file on our
7
LSP
0
7
TCK Counter Status LSP
0
7
Reserved
N
0
7
/GPIO
7
Input
7
Reserved
N
0
7
6
LSP
N
0
6
Reserved
N
0
6
6
Input
/GPIO
TABLE 12. Dedicated GPIO Register
6
Reserved
N
0
(Continued)
6
N
0
6
4
5
Reserved
N
0
5
LSP
N
0
TABLE 13. Shared GPIO Register
5
LSP
N
0
5
Input
5
TABLE 10. Mode Register
TABLE 11. Mode Register
TABLE 9. Mode Register
/GPIO
3
4
TDI
Y
0
5
Reserved
N
0
B
5
4
Reserved
N
0
to TDO
4
LSP
N
0
4
Input
18
4
/GPIO
B
Bits 5 and 6 are optional in the HDL to support five LSPs with
a single Mode Register
added to allow support of up to eight LSPs.
F(x) = X
This signature compactor is used to compress serial data
shifted in from the local scan chain, into a 16-bit signature.
This signature can then be shifted out for comparison with an
expected value. This allows users to test long scan chains in
parallel, via Broadcast or Multi-Cast addressing modes, and
check only the 16-bit signatures from each module. The
LFSR is initialized with a value of 0000 Hex upon reset.
32-BIT TCK COUNTER REGISTER: The 32-bit TCK
counter register enables BIST testing that requires n TCK
cycles, to be run on a parked LSP while another ’STA111
port is being tested. The CNTRSEL instruction can be used
to load a count-down value into the counter register via the
active scan chain. When the counter is enabled (via the
CNTRON instruction), and the LSP is parked, the local TCKs
will stop and be held low when terminal count is reached.
The TCK counter is initialized with a value of 00000000 Hex
upon reset.
Loopback TCK Free Running Disable LSP
4
Reserved
N
0
3
Reserved
N
0
4
3
LSP
N
0
3
Output
16
0
n
3
1
2
/GPIO
(HDL only)
+ X
3
Y
0
n
2
Input (TDI)
Y
0
12
3
Reserved
N
0
3
+ X
2
LSP
Y
0
2
Output
3
+ X + 1
0
2
/GPIO
. A second Mode Register
1
Output (TDO)
Y
0
2
2
LSP
N
0
1
LSP
Y
0
1
Output
7
1
/GPIO
2
Y
0
1
LSP
N
0
1
2
0
Output (TMS)
Y
0
6
0
LSP
Y
0
1
LSP
Y
0
0
Output
1
0
1
0
LSP
N
0
/GPIO
may be
0
LSP
Y
1
5
0
0