SCANSTA111 National Semiconductor Corporation, SCANSTA111 Datasheet - Page 4

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SCANSTA111

Manufacturer Part Number
SCANSTA111
Description
Enhanced Scan Bridge Multidrop Addressable Ieee 1149.1 Jtag Port
Manufacturer
National Semiconductor Corporation
Datasheet

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VCC
GND
TMS
TDI
TDO
TCK
TRST
TRIST
A
Y
S
OE
TDO
TDI
TMS
TCK
B
(0-6)
B
B
(0-2)
Pin Name
B
(0-2)
B
B
(0-2)
(0-2)
B
(B,0-2)
Pins
No.
3
3
1
1
1
1
1
4
1
1
7
1
3
3
3
3
N/A
N/A
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Power
Ground
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
’STA111. Also controls sequencing of the TAPs which are on the local scan chains. This input
has a 25KΩ pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate
method). When the device is power-off (V
load to ground (Note 1). When V
to be a capacitive load with the pull-up to ground.
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA111 through
this input pin. This input has a 25KΩ pull-up resistor and no ESD clamp diode (ESD is
controlled with an alternate method). When the device is power-off (V
appears to be a capacitive load to ground (Note 1). When V
to V
BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA111 and the
local TAPs, back toward the scan master controller. This output has 24mA of drive current.
When the device is power-off (V
load (Note 1).
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the ’STA111 and of the local scan ports. This input has no pull-up
resistor and no ESD clamp diode (ESD is controlled with an alternate method). When the
device is power-off (V
1). When V
load to ground.
TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA111 logic.
This input has a 25KΩ pull-up resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
capacitive load to ground (Note 1). When V
input appears to be a capacitive load with the pull-up to ground.
TRI-STATE NOTIFICATION OUTPUT: This signal is asserted high when the associated TDO
is TRI-STATEd. Associated means TRIST
has 12mA of drive current.
BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y
a single selected LSP. (Not available when multiple LSPs are selected). This input has an
internal pull-up resistor.
BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the
A
has 24mA of drive current.
SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique
address to) each ’STA111 on the system backplane .
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control
signal TRI-STATEs all local scan ports on the ’STA111, to enable an alternate resource to
access one or more of the three local scan chains.
TEST DATA OUTPUTS: Individual output for each of the local scan ports . These outputs
have 24mA of drive current.
TEST DATA INPUTS: Individual scan data input for each of the local scan ports .
TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS
does not provide a pull-up resistor (which is assumed to be present on a connected TMS
input, per the IEEE 1149.1 requirement) . These outputs have 24mA of drive current.
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These
are buffered versions of TCK
n
of a single selected LSP. (Not available when multiple LSPs are selected). This output
SS
) this input appears to be a capacitive load with the pull-up to ground.
DD
TABLE 2. Pin Descriptions
= 0V (i.e.; not floating but tied to V
DD
floating), this input appears to be a capacitive load to ground (Note
4
B
. These outputs have 24mA of drive current.
DD
DD
= 0V or floating), this output appears to be a capacitive
= 0V (i.e.; not floating but tied to V
Description
B
DD
is for TDO
DD
floating), this input appears to be a capacitive
= 0V (i.e.; not floating but tied to V
SS
DD
) this input appears to be a capacitive
B
floating), this input appears to be a
, TRIST
DD
1
= 0V (i.e.; not floating but tied
is for TDO
DD
SS
floating), this input
) this input appears
1
, etc. This output
SS
) this
n
n
of

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