SCANSTA111 National Semiconductor Corporation, SCANSTA111 Datasheet - Page 21

• Manufacturer Part Number: SCANSTA111
• Description: Enhanced Scan Bridge Multidrop Addressable Ieee 1149.1 Jtag Port
• Manufacturer: National Semiconductor Corporation

Special Features
Throught this datasheet, notations exist to clarify the differ-
ences between features available on the Silicon version and
the HDL version.
KNOWN POWER-UP STATE
The STA111 has a known power-up condition. This is the
same state that the device is in after a TRST reset. This
happens at power-up without the presence of a TCK
Reset can also occur via a 5 TMS high reset or a SOFTRE-
SET command.
POWER-OFF HIGH IMPEDANCE INPUTS AND
OUTPUTS
The STA111 backplane test port features power-off high
impedance inputs and outputs.
The TDI
resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
ing), these inputs appear to be a capacitive load to ground.
When V
appear to be capacitive with the pull-up to ground.
The TCK
diode (ESD is controlled with an alternate method). When
the device is power-off (V
a capacitive load to ground. When V
but tied to V
ground.
When the device is power-off (V
TDO
Refer to the device IBIS model on our website for more
details
www.national.com/appinfo/scan/ibis.html.
TRST
TRST
known power-up state.
TRST
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR state the TRST
other states the TRST
PHYSICAL LAYER CHANGES
TRIST for TDO
external buffer circuit between the ’STA111 and the
backplane/LSP. This would allow, for example, a CMOS-to-
LVDS converter to drive an LVDS JTAG backplane test bus.
These signals are always driving. A seperate TRIST is pro-
vided for each LSP to report a TRI-STATE on TDO when the
LSP is not in a shift state.
SVF DRIVEN, SELF-CHECKING TEST BENCH
The STA111 consists of 3 types of pins, dot1 backplane pins,
dot1 LSP pins and support pins. The command interpreter of
the test bench is able to translate a limited set of SVF
• Number/Type of GPIO bits: The STA111 has both dedi-
cated and shared GPIO (General Purpose I/O). Each
dedicated group of GPIO bits supports from 0 to 4 dedi-
cated inputs and 0 to 4 dedicated outputs. There are
provisions for specifying the default (power-up) value.
TMS
pins functioning as LSP or GPIO. TMS
outputs, TDI
B
B
n
output appears to be a capacitive load.
: TRST
: Assertion of TRST
DD
(0-n)
B
B
, TMS
about
= 0V (i.e.; not floating but tied to V
input has no pull-up resistor and no ESD clamp
, TDO
SS
n
) the input appears to be a capacitive load to
n
B
is an output on the LSP side of the STA111.
B
, and TRST
is an input in the GPIO mode.
(0-n)
the
and TDO
n
and TDI
pin will be driven high.
DD
I/O
B
floating), the input appears to be
will return the device back to its
n
n
B
(Continued)
are signals for enabling an
pin will be driven low. In all
inputs have a 25KΩ pull-up
characteristics
(0-n)
DD
DD
are also dual purpose
= 0V or floating), the
= 0V (i.e.; not floating
n
SS
and TDO
) these inputs
at
DD
B
.
http://
n
float-
are
21
commands to the dot1 backplane pins. The SVF shift com-
mands contain both the stimulus (TDI
sponse (TDO
The interpreter is able to parse the following commands:
ENDDR, ENDIR, RUNTEST, SDR, SIR, STATE, TRST.
PASS-THROUGH PINS
Each LSP may selectively have two pass-through pins. The
pair of pass-through pins consist of an input (A
output (Y
level being received by the backplane pass-through input
(A
drives the backplane pass-through output (Y
The Pass-through pins are available only when a single LSP
is selected. For each LSP these pins will be enabled when
the level 2 protocol state-machine is not in the Parked-TLR
state. When not enabled they are TRI-STATED.
LSP GATING
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR state, the four LSP signals shall be controlled
as shown in Table 14 below. Upon entry into the Parked-TLR
state (power-up, reset, PARKTLR or GOTOWAIT) a counter
in the LSP state-machine allows 512 TCK
occur on TCK
logic 0.
Letting 512 TCK
high TMS reset to occur on over 100 levels of hierarchy
before the STA111 gates TCK
running clock system).
The STA111 does not require that any clock pulses are
received on TCK
Setting Bit 3 of Mode Register
Parked-RTI,
states. Default is free-running (bit 3 = 0). The value stored in
bit 3 of Mode Register
512 clock pulses before gating TCK
state. (See section on Mode Register
IEEE 1149.4 SUPPORT
The STA111 provides support for a switched analog bus.
Each
(LSP_ACTIVE
Parked-TLR and high (1) otherwise. This signal can be used
to enable/disable analog switches external to the STA111.
GPIO CONNECTIONS
General Purpose I/O (GPIO) pins are registered inputs and
outputs that are parameterized in the HDL. The two types of
GPIOs than can be used in the STA111 are described in the
next two sections.
DEDICATED: Each LSP supports up to four (4) dedicated
inputs and up to four (4) dedicated outputs. These are sep-
erate, dedicated GPIO signals controlled by dedicated GPIO
LSP
Connection
TDO
TMS
TDI
TCK
B
). Conversly, the level on the LSP pass-through input (A
n
n
n
n
LSP
n
). The LSP pass-through output (Y
TABLE 14. Gated LSP Drive States
B
n
(0-2)
).
has
Parked-Pause-DR
Drive State
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
TCK
before gating. Once gated, TCK
B
B
pulses pass through to TCK
) which is low (0) when the LSP is in
while in the Parked-TLR state.
B
an
for 512 pulses, then gated LOW
0
does not effect the requirement of
unparked-TLR
0
n
to 1 gates TCK
(for power saving in a free-
and
0
n
).
B
) and expected re-
in the Parked-TLR
B
Parked-Pause-IR
notification
clock pulses to
B
).
n
n
n
n
allows a five
) drives the
when in the
www.national.com
will drive a
n
) and an
pin
n
)