SCAN25100TYA/NOPB National Semiconductor, SCAN25100TYA/NOPB Datasheet
SCAN25100TYA/NOPB
Specifications of SCAN25100TYA/NOPB
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SCAN25100TYA/NOPB Summary of contents
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... Exceeds LV and HV CPRI voltage and jitter requirements ■ 2457.6, 1228.8, and 614.4 Mbps operation ■ Integrated delay calibration measurement (DCM) directly measures T14 and Toffset delays to Block Diagram © 2008 National Semiconductor Corporation ■ DCM also measures chip and other delays to accuracy ■ Deterministic chip latency ■ ...
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Pin Diagram www.national.com SCAN25100 (Top View) 100–Pin TQFP with Exposed Ground Pad Order Number SCAN25100TYA See NS Number VXF100B 2 20183402 ...
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Pin Descriptions Pin # Pin Name I/O, Type HIGH SPEED DIFFERENTIAL I/O 12 DOUTP O, CML 11 DOUTN 18 RINP I, CML 17 RINN PARALLEL DATA BUS 65 DIN [0] I, LVTTL or 1.8V 66 DIN [1] LVCMOS Internal 67 ...
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Pin # Pin Name I/O, Type 79 CDET O, LVTTL or 1.8V LVCMOS CONTROL PINS 82 PE [0] I, LVTTL or 1. [1] LVCMOS Internal pull down 88 EQ [0] I, LVTTL or 1. [1] LVCMOS ...
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Pin # Pin Name I/O, Type 96 SPMODE [0] I, LVTTL or 1.8V 97 SPMODE [1] LVCMOS Internal pull down 98 TENBMODE I, LVTTL or 1.8V LVCMOS, Internal pull down 99 LOOP [0] I, LVTTL or 1.8V 100 LOOP [1] ...
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Pin # Pin Name I/O, Type GROUND DAP 101 GND I, Ground Note: I= input O = output Internal pull down = input pin is pulled low by an internal resistor resistor www.national.com Description Device ground. Pad must be soldered ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (AV ) DD18 Supply Voltage (PV , IOV ) DD DD Supply Voltage (AV ) DD33 LVCMOS Input Voltage LVCMOS Output Voltage MDC/MDIO/ADD[0:4],VSEL Input Voltage −0.3V to (AV ...
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Symbol Parameter JTAG DC SPECIFICATIONS (3.3V I/O) V High level input voltage IH V Low level input voltage IL I Input Current IN V High level output voltage OH V Low level output voltage OL C Input/Output Capacitance IO MDIO/MDC/ADD0-4 ...
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Symbol Parameter TRANSMITTER SERIAL TIMING SPECIFICATIONS V Output differential voltage swing OD R Output differential resistance DO R Output Return Loss Serial data output transition time R F (Notes 12, 16) JIT Serial data output deterministic ...
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Symbol Parameter RECEIVER OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1, 1228.8 and 614.4 Mbps only) t RXCLK Propagation Delay PDRX t Duty cycle DC f RXCLK input frequency RXCLKR Output data transition time R F RECEIVER OUTPUT TIMING ...
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Symbol Parameter JTAG TIMING SPECIFICATIONS f JTAG TCK Frequency JTAG t TDO data transition time (20% to R-J 80%) t F-J t Setup Time TDI to TCK High or Low S-TDI t Hold Time TDI to TCK High or Low ...
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AC Timing Diagrams www.national.com READ MODE 20183409 WRITE MODE 20183410 12 ...
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Functional Description POWER UP AND LINK SYNCHRONIZATION An internal power on reset (POR) circuit disables the trans- mitter output and sets receiver ROUT[9:0], LOS, LOCKB, and CDET in static high state for approximately 150 ms (150ms is based on an ...
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Reset Type Initial power up ≥ TXPWDNB and RXPWDNB low for ≥ RESETB low for 1 us Write “0” to MDIO RESETB register SPMODE change ≥ TXCLK missing for 7 cycles ≥ RXCLK missing for 7 cycles (Read Mode) TRSTB ...
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DCM. Pin Type RXCLK (write mode) 1.8V CMOS or LVTTL SYSCLK LVDS SYSCLK can be used to synchronize remote radio heads since it provides a local 30.72 MHz internal ...
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TRANSMIT DATA DIN[9:0] Transmit Parallel Input Data Transmit input data pins DIN[9:0] are latched on both rising and falling edges of TXCLK. By using both TXCLK edges, the Tx Input 10-bit Mode (TENBMODE = 1) DIN[0] Coded Data Bit DIN[1] ...
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FIGURE 4. SCAN25100 Serial Input Connection Receive Equalization The receiver front-end provides 3 steps of equalization filter to compensate for ISI deterministic jitter from lossy back- EQ[1] EQ[ Equalization disabled Equalization (approximately 2 dB ...
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WRITE MODE (RXCLKMODE = 0) In write mode, RXCLK is the recovered clock output. The pins ROUT[9:0], CDET, LOCKB, and LOS are synchronous to RXCLK. READ MODE (RXCLKMODE = 1) In read mode, RXCLK is an input and the pins ...
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FIGURE 6. Radio Equipment (RE) Clock Syncronization In multi-hop applications, using a jitter cleaner between SysCLK and RefCLK is recommended to attenuate any ac- cumulated jitter (< 5 MHz). RECEIVER PLL LOCK DETECTION The LOCKB pin indicates the lock status ...
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LOF (LOSS OF FRAME) DETECTION LOF counter is provided through an LOF MDIO status register per CPRI Specification. The LOF function is disabled in 10- bit mode. Under 8-bit mode, LOF will prevent the SCAN25100 DCM scheme from activating. Delay ...
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MDIO Serial Control Interface The MDIO serial control interface allows communication be- tween a station management controller and SCAN25100 de- vices. MDIO and MDC pins are 3.3V LVTTL compliant, not 1.2V compatiable software compatible with the station management ...
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A normal write operation uses the <01>. The data is latched in the SCAN25100 on each edge of the MDC clock. MDIO is sourced from the station side of the MDIO control interface. www.national.com FIGURE 7. Typical MDIO/MDC Read Operation ...
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Register Description The SCAN25100 implements the device (0x1E.) Oth- er registers defined by 802.3ae-2002 may not be implement SCAN25100. The SCAN25100 has a rich MDIO register set to allow the chip to be controlled and ...
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... SCAN25100 into a low power mode. Access Bit Description RO National Semiconductor identifier assigned by the IEEE. Access Bit Description RO National Semiconductor identifier assigned by the IEEE. RO SCAN25100 device identifier (3Eh). RO SCAN25100 revision number. Access Bit Description — Reserved for future use. Returns undefined value when read. ...
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Transmit De-Emphasis Address: 06h Value: 2000h Bit Default Bit Name D15–D8 8'h20 Hyperframe Size D7-D2 6'd0 Reserved D1-D0 2'b00 TX DE Loopback Mode Address: 07h Value: 0000h Bit Default Bit Name D15–D4 12'h000 Reserved D3-D0 4'b0000 Loopback 4'b0000 4'bxx10 4'bxxx1 ...
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Speed Mode Address: 0Ah Value: 0000h Bit Default Bit Name D15–D2 14'd0 Reserved D1-D0 2'd0 SPMODE BIST Status Address: 0Bh Value: 0100h Bit Default Bit Name D15-D13 3'd0 Reserved D12 1'b1 BIST Stopped D11 1'b0 BIST Error D10 1'b0 BIST ...
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Loss of Signal (LOS) Address: 11h Value: 0000h Bit Default Bit Name D15–D9 7'd0 Reserved D8 0'b0 LOS Status D7-D0 8'd0 LOS Count Deserializer Loss of Lock Address: 12h Value: 0000h Bit Default Bit Name D15–D8 8'd0 Reserved D7-D0 8'd0 ...
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Misc Status 2 Address: 14h Value: 0000h Bit Default Bit Name D15–D8 8'd0 Reserved D7 RXCDR Lock - Ready D6-D2 Reserved D1 TXPLL Lock - Ready D0 TXPLL Counter Start of Hyperframe Character Address: 15h Value: 01BCh Bit Default Bit ...
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DCM Address: 19h Value: 0000h Bit Default Bit Name D15-D12 4'h0 Reserved D11 1'b0 Hyperframe Length Enable D10-D9 2'b00 Initial Power up wait cycle 2'b00 2'b01 2'b10 2'b11 D8-D1 7'd0 Reserved D0 1'b0 Enable DCM Reserved Address: 1Ah 1Bh 1Ch ...
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Tser Lower Address 22h Value: 0000h Bit Default Bit Name D15–D0 16'd0 Tser Lower Tser Upper Address 23h Value: 0000h Bit Default Bit Name D15–D6 10'd0 Reserved D5 1'd0 Reserved D4–D0 5'd0 Tser Upper Tdes Lower Address 24h Value: 0000h ...
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... This high-speed operation is achieved without significant layout and overall PCB design constraints. However, adhering to a few specific layout guide- lines will optimize signal integrity and performance. The fol- lowing list of topics is covered in National Semiconductor AN-1463. Access Bit Description RO Lower 16 Tout-in DCM bits ...
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Physical Dimensions See www.national.com/quality/marking_conventions.html for additional part marking information www.national.com inches (millimeters) unless otherwise noted 100-Pin TQFP with Exposed Ground Pad (Top View) Order Number SCAN25100TYA NS Package Number VXF100B 32 ...
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Notes 33 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...