FIN324C Fairchild Semiconductor, FIN324C Datasheet - Page 9

• Manufacturer Part Number: FIN324C
• Description: ?serdes? Fin324c ? 24-bit Ultra-low Power Serializer / Deserializer Supporting Single And Dual Displays
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.9
Application Diagrams
Baseband
Processor
Baseband
Processor
DATA[17:0]
R,G,B[5:0]
Figure 9.
GPIO
RESET 0
RESET 1
GPIO
CKSEL
CKSEL
/STBY
/STBY
Hsync
Vsync
PCLK
SCLK
SDAT
/RES
/RES
/CS1
R/W
/CS0
D/C
/CS
SD
D/C
Figure 8.
VDDP1
VDDP1
R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display
D4:G6
D4:G6
Notes:
Notes:
G3
G2
C4
C3
D3
G3
G2
A4
B4
C4
C3
A3
B3
A2
B2
A1
D3
B1
A4
B4
A3
B3
A2
B2
A1
F3
B1
F3
(Continued)
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
Dual Display with RGB Main Display and SPI Sub-Display Interface
STRB0
STRB1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
VDDP VDDS/A
STRB0
STRB1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
VDDP VDDS/A
VDDP1
VDDP1
C2
C2
R/W interface. R/W signal connected to baseband microprocessor.
Unused slave output pin must be NC (No Connection).
PAR/SPI connected HIGH to indicate parallel operation.
Pin numbers for BGA package.
Write-only interface (R/W hardwired LOW).
SPI sub-display interface PAR/SPI=LOW for both master and slave.
SCLK connected to CNTL[5]; SDAT connected to CNTL[4].
Shared data pin SDAT; SCLK connections on sub-display.
Unused slave output pin must be NC (No Connection).
Pin numbers for BGA package.
Master
Master
VDDS/A
VDDS/A
E2
E2
CKS-
CKS+
CKS+
CKS-
GND
GND
GND
GND
GND
GND
DS+
DS+
DS-
DS-
F2
F2
E3
D2
C1
D1
E1
G1
F1
D1
E1
G1
F1
E3
D2
C1
.
G1
F1
D1
E1
G1
F1
D1
E1
E3
D2
C1
E3
D2
C1
9
GND
GND
GND
GND
GND
GND
VDDP VDDS/A
CKS+
CKS-
DS+
DS-
C2
CKS+
CKS-
DS+
DS-
VDDP2
C2
VDDP2
VDDP VDDS/A
Slave
Slave
DP[17:0]
PAR/SPI
PAR/SPI
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
WCLK0
WCLK1
WCLK0
WCLK1
E2
.
SLEW
E2
VDDS/A
VDDS/A
SLEW
VDDP
VDDP
/RES
/RES
R/W
M/S
R/W
M/S
F2
F2
.
A4
B4
D4:G6
C4
C3
A3
B3
A2
B2
A1
D3
F3
G3
G2
B1
A4
B4
D4:G6
C4
C3
A3
B3
A2 NC
B2 NC
A1 NC
D3
F3
G3
G2
B1
NC
NC
NC
F6 SCLK DP[6]
E5 SDAT DP[7]
VDDP2
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
Edge Rate Control Option
SLEW must be connected
to VDDP or GND for low
power.
DATA [17:0]
D/C
/CS0
RESET 0
P/S
/CS1
DATA[17:0]
D/C
RESET 1
R/W
Main Display
Sub- Display
SCLK
SDAT
/CS
D/C
RESET
P/S
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
Sub- Display
Main Display
Module 1
Module 1
www.fairchildsemi.com