FIN324C Fairchild Semiconductor, FIN324C Datasheet - Page 14

• Manufacturer Part Number: FIN324C
• Description: ?serdes? Fin324c ? 24-bit Ultra-low Power Serializer / Deserializer Supporting Single And Dual Displays
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.9
Notes:
4.
5.
6.
7.
8.
9.
10. Assumes propagation delay across the flex cable and through the I/Os of 20ns.
11. Total read latency t
12. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable
13. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable
14. SPI-Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
15. Timing allows the device to completely reset prior to powering down.
16. Internal reset filter allows assertion prior to completion of read or write date transfer.
17. Timing ensures that last write transaction is complete prior to going into standby.
18. V
19. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that
20. STRBn must be held off until internal oscillator has stabilized.
t
Symbol
t
VDD-SKEW
t
RES-STBY
VDD-RES
t
DVALID
Characterized, but not production tested.
Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction.
Indirectly tested through serial clock frequency and serial data bit tests.
Pulse width low WCLKn measurements are measured at 30% of V
SLEW=1.
Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator
frequency.
Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
across the flex cable and I/O propagation delays.
latency (t
flight times and I/O propagation delays.
flight times and I/O propagation delays.
across the flex cable and I/O propagation delays.
consumed. Guaranteed by characterization.
/RES be held low during the power supply ramp.
DDA/S
Allowed Skew between V
and V
Minimum Reset Low Time
After V
/STBY Wait Time After /RES ↑
/STBY to Active Edge of
Strobe
must power up together. V
PD-RDD
DDA/S
DD
). t
Parameter
Stable
(18)
PD-RD
PD-RD
= t
is the sum of the Read-Control Phase latency (t
PD-RDC
DDP
+ t
DDP
PD-RDD
Figure 18
M/S=0 /STBY=1, /RES=↑
Figure 18
M/S=1 /RES=1, /STBY= ↑
Figure 18
M/S=0 /RES=1
Figure 18
may power-up relative to V
.
Test Conditions
(20)
14
(19)
DDA/S
DDP
in any order without static power being
. Measurements apply when SLEW=0 or
PD-RDC
Min.
-∞
20
20
30
) and the Read-Data Phase
Typ.
Max.
+∞
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Unit
ms
µs
µs
µs