FIN324C Fairchild Semiconductor, FIN324C Datasheet - Page 5

• Manufacturer Part Number: FIN324C
• Description: ?serdes? Fin324c ? 24-bit Ultra-low Power Serializer / Deserializer Supporting Single And Dual Displays
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.9
System Control Pins
(M/S) Master / Slave Selection: A given device can be
configured as a master or slave device based on the
state of the M/S pin.
Table 1. Master/Slave
(PAR/SPI) SPI Mode Selection: The PAR/SPI signal
configures STRB0(WCLK0) for SPI mode write operation.
STRB1(WCLK1) always operates in parallel mode.
Control signals CNTL[5:0] all pass in SPI mode. In SPI
mode, the SCLK signal is used to strobe the serializer.
SPI mode supports SPI writes only.
Table 2. Channel 0 PAR/SPI Configuration
(CKSEL) Strobe Selection Signal: The CKSEL signal
exists only on the master device and determines which
strobe signal is active. The active strobe signal is
selected by CKSEL and PAR/SPI inputs.
Table 3. PAR/SPI
PAR
PAR
/SPI
/SPI
0
1
0
0
1
1
M/S=1 MASTER
CKSEL
SDAT=CNTL[4]
SCLK=CNTL[5]
Parallel Mode
M/S
/CS=STRB0
0
1
0
1
0
1
SPI Mode
CNTL[5]
Source
Master
Strobe
STRB1
STRB0
STRB1
SDAT=DP[7] & CNTL[4]
SCLK=DP[6] & CNTL[5]
M/S=0 SLAVE
Parallel Mode
/CS=WCLK0
Configuration
Master Mode
SPI Mode
DP[6] & CNTL[5]
Slave Mode
Slave Strobe
WCLK1
WCLK0
WCLK1
Source
5
(/RES, /STBY) Reset and Standby Mode Functionality:
Reset and standby mode functionality is determined by
the state of the /RES and /STBY signals for the master
device and the /RES and internal standby-detect signal
for the slave device. The /RES control signal has a filter
that rejects spurious pulses on /RES.
Table 4. Reset and Standby Modes
Note:
2.
Table 5. Reset and Standby Mode States
(SLEW) Slew Control: The slew control operates only
when in slave mode. This signal changes the edge rate
of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0
signals to optimize edge rate for the load being driven.
Master read mode outputs have “slow” edge rates. See
the AC Deserializer Specifications table for “slow” and
“fast” edge rates.
Table 6. Slew Rate Control
DP[17:0]
CNTL[5:0]
STRB[0:1]
(WCLK[0:1])
/RES
0
1
1
The slave device is put into standby mode through
control signals sent from the master device.
Pin
/STBY (SLEW)
/STBY
0
1
X
0
1
Reset / Standby
(2)
Disabled
Disabled
Disabled
Master
Reset Mode
Operating
Standby
Master
Mode
Mode
Slave M/S=0
Reset
Slave
High
Low
Low
“Slow”
“Fast”
Reset Mode
Operating
Standby
Mode
Slave
Mode
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Last data
Last data
Standby
(3)
Slave
High