FIN324C Fairchild Semiconductor, FIN324C Datasheet - Page 6

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FIN324C

Manufacturer Part Number
FIN324C
Description
?serdes? Fin324c ? 24-bit Ultra-low Power Serializer / Deserializer Supporting Single And Dual Displays
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.9
CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES,
/STBY(SLEW), PAR/SPI, and CKSEL. For connectivity
flexibility, these signals are over-voltage tolerant to the
maximum supply voltage connected to the device. This
allows these signals to be tied HIGH to either a V
V
signals are all CMOS inputs and should never be
allowed to float.
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild’s
proprietary differential CTL I/O technology. During data
transfers, the serial I/O are powered up to a normal
operating mode around .5V. Upon completion of a data
transfer, the serial I/O goes to a lower power mode
around V
Table 7. Serial Pin Orientation
G
E
D
C
B
A
DDP
F
Package
6
MLP
BGA
supply without static current consumption. These
Master
BGA
5
DDS
4
.
3
CKS+
CKS-
Figure 4.
DS+
DS-
2
CKS+
1
D1
2
Master (M/S=1) (Pad/Pin #)
1
BGA Pair
<DS+>
<DS->
<CKS->
<CKS+>
CKS-
2
E1
3
3
4
Slave
BGA
5
DS-
6
F1
6
A
D
E
B
C
F
G
DDS
or
21
22
23
24
25
26
27
28
29
30
6
DS+
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0],
CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals.
These signals have built-in voltage translation, allowing
the signals of the master and slave to be connected to
different V
Serial I/O Orientation Logic
The serial I/O signal traces should not cross between
the master and the slave. The pin locations have been
designed to eliminate the need to cross traces. See
Table 7, Figure 4 and Figure 5.
G1
Master
7
MLP
DDP
CKS+
CKSEL(H)
PAR/SPI
G1
VDD S
VDDA
supply voltages.
CKS+
7
CKS-
/RES
DS+
M/S
DS-
Figure 5.
10
9
8
7
6
5
4
3
2
2
1
Slave (M/S=0) (Pad/Pin #)
CKS-
F1
6
MLP Pair
1
2
3
4
5
6
7
8
9
10
CKSEL(H)
(DS+)
(DS-)
VDD S
VDD A
(CKS-)
(CKS+)
/RES
PAR/SPI
M/S
DS-
E1
3
www.fairchildsemi.com
Slave
MLP
DS+
D1
2
30
29
28
27
26
25
24
23
22
21

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