FIN324C Fairchild Semiconductor, FIN324C Datasheet - Page 3

• Manufacturer Part Number: FIN324C
• Description: ?serdes? Fin324c ? 24-bit Ultra-low Power Serializer / Deserializer Supporting Single And Dual Displays
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.9
Pin Definitions
Note:
1.
CNTL[5:0]
PAR/SPI
DP[17:0]
WCLK0
WCLK1
CKSEL
STRB0
STRB1
/STBY
SLEW
VDDP
VDDS
VDDA
SCLK
SDAT
CKS+
/RES
CKS-
GND
R/W
Pin
DS+
M/S
DS-
/CS
Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave.
I/O Type
Differential
Differential
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS IN
CMOS IN
CMOS IN
CMOS IN
CMOS IN
CMOS IN
CMOS IN
Serial I/O
Serial I/O
Supply
Supply
Supply
Supply
CMOS
OUT
# Pins
1-3
18
1
1
1
1
1
1
6
1
2
2
2
2
2
1
1
1
Master/Slave Control Input:
The master is tied to the processor. The slave is tied to the display(s).
M/S=1 MASTER, M/S =0 SLAVE
Reset and power-down signal
/RES=0: Resets and powers down all circuitry
/RES=1: Device enabled
Master standby signal
/STBY=0: Device powered down
/STBY=1: Device enabled
Slave output slew rate control
SLEW=1: Fast edge rate
SLEW=0: Slow edge rate
Parallel / SPI display interface select
PAR/SPI=1: Parallel Interface
PAR/SPI=0: SPI Interface using STRB0 and WCLK0
Master clock source select input.
CKSEL=1: STRB1 and WCLK1 Active
CKSEL=0: STRB0 and WCLK0 Active
Parallel data I/O.
I/O direction controlled by M/S pin and R/W internal state.
DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only)
DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only)
Parallel data I/O. I/O direction controlled by M/S pin
M/S=1: Inputs
M/S=0: Outputs
Read / Write input control or output signal.
M/S=1: Input
M/S=0: Output
Functional operation:
R/W=1: Read
R/W=0: Write
Word latch or pixel clock input.
Word latch or pixel clock output.
SPI mode signal pins.
The master SCLK input is shared with CNTL[5] when M/S=1 and PARI/SPI=0.
The master SDAT input is shared with CNTL[4] when M/S=1 and PARI/SPI=0.
The master /CS input is shared with STRB0 when M/S=1 and PAR/SPI=0.
The slave SCLK output is shared with DP[6] and CNTL[5] when M/S=0 and PAR/SPI=0.
The slave SDAT output is shared with DP[7] and CNTL[4] when M/S=0 and PAR/SPI=0.
The slave /CS output is shared with WCLK0 when M/S=0 and PAR/SPI=0.
Serial clock differential signal
Serial data differential signal
Power supply for parallel I/O and internal circuitry.
Power supply for serial I/O.
Power supply for internal bit clock generator.
Ground Pins:
BGA - C1 and D2; E3 is for supplier use only and must be tied to ground.
MLP - center pad; Pin 12 is for supplier use only and must be tied to ground.
3
(1)
(1)
Description of Signals
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