STV2050A STMicroelectronics, STV2050A Datasheet - Page 52

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STV2050A

Manufacturer Part Number
STV2050A
Description
IC DGTL CONVERGENCE PROC 80-PQFP
Manufacturer
STMicroelectronics
Type
Videor
Datasheet

Specifications of STV2050A

Applications
HDTV
Mounting Type
Surface Mount
Package / Case
80-MQFP, 80-PQFP
Case
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
STV2050A - CONVERGENCE
Figure 28. Convergence Channel Structure
Calibrated sources are used to generate the reference current for all CONVERGENCE and
FOCUS DACs.
The reference current is defined as
page
The outputs can be disabled using the CDO bit in the E3 register.
Notes:
1. The CDO bit is a common control for the convergence AND the focus outputs.
2. The CDN bit must be set to 1 for normal operation. Refer to
In order to perform a “soft” start of the convergence to avoid damaging the amplifiers, a “Soft
Switch On” of the DACs is carried out digitally by applying a reduced digital gain (reduction by
factor 2) for at least 1 field after the DACs have been switched on from high impedance to
normal operation (using the CDO bit) or when the DACs have been previously switched to the
offset values by the slave bus.
52/83
SALES SERVICE, LAB TRIAL MODES" on page
61.)
CDO
0: High impedance
1: Normal operation.
Iref
-------- -
2
. (Refer to
49.
Section 13 "CURRENT REFERENCE" on
Section 9.7 "MANUFACTURING, AFTER-
DNxx
DAxx
+
-

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