STV2050A STMicroelectronics, STV2050A Datasheet - Page 26

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - TIMEBASES
5.4.2 Field Parity Recognition
In the case of a standard STV2050A implementation, synchronization is achieved using sig-
nals extracted horizontally (Line Flyback) and vertically (Frame Flyback). Unfortunately, de-
pending on the components and the configuration, the phase relationship between these sig-
nals is not the same in every TV chassis. In this case, field parity recognition can be unreliable
unless special features are implemented. The STV2050A can achieve perfect field parity rec-
ognition using the “Vertical Sync shifT“ (VST).
When the VST[7:0] bits in the DA register are set to the optimum value, the STV2050A distin-
guishes perfectly between the two fields. This is used to control the interpolation of the con-
vergence values and the video pattern generator according to the interlaced scanning
scheme.
The correct VST value can be evaluated by measuring the timing of the vertical pulse. This
timing is measured by the STV2050A, and the results are stored in the S13[7:0] and S14[7:0]
bits in the E6 register.
In non-interlaced mode, field recognition can be switched off by the IIE bit in the DA register.
5.4.3 Field Counter
A 4-bit field counter is implemented for controlling the optical alignment procedure. The
counter value is stored in the S12[3:0] bits in the E5 register (read only).
This counter will be reset to 0000 at IC power-up and will be incremented after every vertical
reset. The counter will overflow from 1111 to 0000. (The counter will not be reset when the E5
register is read.)
5.4.4 Convergence Correction Frame Retrace
This is the time interval defined as follows:
– Start at grid line number 11 + DCB[7:0] bits in the DB register,
– Stop at 2 TV lines after the frame pulse + DCT[8:0] bits in the DB register;
where DCB and DCT are the number of TV lines.
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IIE
0 = Interlace OFF
1 = Interlace ON