STV2050A STMicroelectronics, STV2050A Datasheet - Page 24

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - TIMEBASES
the corresponding convergence correction value is defined by the Horizontal DAC phase
HDP[6:0] value in the DB register.
The following range for the horizontal DAC phase is allowed:
The timing of the DAC output leads the most if HDP is equal to zero.
Figure 11. Horizontal DAC Phase
5.3.2 Horizontal Width Adjustment
In order to fit the video pattern into the full visible area of the screen, the width of the pattern
may be adjusted. Horizontal width adjustment is done by changing the number of clock cycles
between the vertical grid lines during retrace and the visible grid. The timing for the corre-
sponding DAC values is changed accordingly. Refer to
ment" on page
5.3.3 Auto-Calibration of DACs
All the DACs of the STV2050A can be automatically calibrated. This feature ensures a high
matching stability in both time and temperature. The process involves the sequential calibra-
tion of 120 cells.
To ensure optimal results, each cell must be calibrated at least every 4 ms.
The duration of one cell calibration must be greater than 2us. This duration is controlled by the
internal “calibration clock”. The calibration clock is generated using a divider of the system
clock. (Refer to
vision ratio is programmable via the ACL[1:0] bits in D8.
24/83
0
35.
Section 5.1 "LINE LOCKED PLL AND SYSTEM CLOCK" on page
HGN
HGRID
coil
current
DAC
output
HDP
2
HGD
n-3
n-2
n-2
n-1
HGD HGD
n-1
n
HDP
n+1
n
Section 7.2.1 "Horizontal Grid Adjust-
n+1 n+2 n+3
n+2
n+3 n+4
22). The di-