ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 9

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. Memories
7.1
7.2
8386A–AVR–07/11
Features
Overview
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•
•
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The Atmel
Data Memory. Executable code can only reside in the Program Memory, while data can be
stored both in the Program Memory and the Data Memory. The Data Memory includes both
SRAM, and EEPROM Memory for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching.
The available memory size configurations are shown in
addition each device has a Flash memory signature rows for calibration data, device identifica-
tion, serial number etc.
Non Volatile Memory (NVM) spaces can be locked for further write and read/write operations.
This prevents unrestricted access to the application software.
Flash Program Memory
Data Memory
Production Signature Row Memory for factory programmed data
User Signature Row
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– CRC Generator support for CRC check of a selectable flash program memory section
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
– I/O Memory
– Bus arbitration
– Separate buses for SRAM, EEPROM, and I/O Memory
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
Byte and page accessible
Optional memory mapping for direct load and store
Configuration and Status registers for all peripherals and modules
16bit-accessible General Purpose Register for global variables or flags
Safe and deterministic handling of priority between CPU, DMA Controller, and other bus
masters
Simultaneous bus access for CPU and DMA Controller
®
AVR
®
architecture has two main memory spaces, the Program Memory and the
”Ordering Information” on page
XMEGA A3U
2. In
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