ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 26

no-image

ATxmega256A3U

Manufacturer Part Number
ATxmega256A3U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256A3U

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega256A3U-AU
Manufacturer:
TI
Quantity:
12 000
Part Number:
ATxmega256A3U-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATxmega256A3U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATxmega256A3U-MH
Manufacturer:
PANASONIC
Quantity:
1 450
Company:
Part Number:
ATxmega256A3U-MH
Quantity:
5 000
14. Interrupts and Programmable Multi-level Interrupt Controller
14.1
14.2
14.3
Table 14-1.
8386A–AVR–07/11
Program Address
(Base Address)
Features
Overview
Interrupt vectors
0x000
0x002
0x004
Reset and Interrupt Vectors
Source
RESET
OSCF_INT_vect
PORTC_INT_base
Atmel
signal a change of state in peripherals, and this can be used to alter program execution. Periph-
erals can have one or more interrupts, and all are individually enabled and configured. When an
interrupt is enabled and configured, it will generate an interrupt request when the interrupt condi-
tion is present. The Programmable Multi-level Interrupt Controller (PMIC) controls the handling
and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC,
the program counter is set to point to the interrupt vector, and the interrupt handler can be
executed.
All peripherals can select between three different priority levels for their interrupts; low, medium
and high. Interrupts are prioritized according to their level and their interrupt vector address.
Medium level interrupts will interrupt low level interrupt handlers. High level interrupts will inter-
rupt both medium and low level interrupt handlers. Within each level, the interrupt priority is
decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low level interrupts have an optional round-robin scheduling scheme to
ensure that all interrupts are serviced within a certain amount of time.
Non-Maskable Interrupts (NMI) is also supported and can be used for critical functions. If a boot-
loader is used, it is possible to move the interrupt vectors from the Application Section to the
Boot Loader Sections so interrupts can be used and executed also during self-programming.
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address
for specific interrupts in each peripheral. The base addresses for the XMEGA A3U devices are
shown in
described for each peripheral in the XMEGA AU manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in
address.
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved from the Application Section to the Boot Loader Section
– Interrupt prioritizing according to level and vector address
– 3 selectable interrupt levels for all interrupts: Low, Medium and High
– Selectable round-robin priority scheme within low level interrupts
– Non-Maskable Interrupts for critical functions
®
AVR
Table
®
XMEGA
14-1. Offset addresses for each interrupt available in the peripheral are
®
have a Programmable Multi-level Interrupt Controller (PMIC). Interrupts
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Table
14-1. The program address is the word
XMEGA A3U
26

Related parts for ATxmega256A3U