ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 25

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13. WDT - Watchdog Timer
13.1
13.2
8386A–AVR–07/11
Features
Overview
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The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It
makes it possible to recover from error situations such as run-away or dead-lock code. The WDT
is a timer, configured to a predefined timeout period and is constantly running when enabled. If
the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is
reset by executing the WDR (Watchdog Timer Reset) instruction from the application code.
The window mode makes it possible to define a time slot window inside the total timeout period
where WDT must be reset within. If the WDT is reset too early or too late and outside this win-
dow, a system reset will be issued. Compared to the normal mode, this can also catch situations
where a code error also causes constant WDR execution.
The WDT will run in Active mode and all sleep modes if enabled. It is asynchronous and runs
from a CPU independent clock source, and will continue to operate to issue a system reset even
if the main clocks fail. The Configuration Change Protection mechanism ensures that the WDT
settings cannot be changed by accident. For increased safety, a fuse for locking the WDT set-
tings is available.
Issues a device reset if the timer is not reset before its timeout period
Asynchronously operation from dedicated oscillator
11 selectable timeout periods, from 8ms to 8s.
Two operation modes
Configuration lock to prevent unwanted changes
– 1kHz output of the 32kHz Ultra Low Power oscillator
– Normal mode
– Window mode
XMEGA A3U
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