ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet
ATxmega256A3U
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... Optical ® ® ® AVR XMEGA 8/16-bit Microcontroller 2 C and SMBus compatible) • Low power battery applications • Power tools • HVAC • Utility metering • Medical applications 8/16-bit Atmel XMEGA A3U Microcontroller ATxmega256A3U ATxmega192A3U ATxmega128A3U ATxmega64A3U Preliminary 8386A–AVR–07/11 ...
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... Ordering Code Flash (Bytes) EEPROM (Bytes) SRAM (Bytes) ATxmega256A3U-AU 256K + 8K ATxmega192A3U-AU 192K + 8K ATxmega128A3U-AU 128K + 8K ATxmega64A3U-AU 64K + 4K ATxmega256A3U-MH 256K + 8K ATxmega192A3U-MH 192K + 8K ATxmega128A3U-MH 128K + 8K ATxmega64A3U-MH 64K + 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. ...
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Pinout/Block Diagram Figure 2-1. Block diagram and pinout Power/Ground Digital function Analog function PA3 1 PA4 2 PA5 3 AREF PA6 4 ADC AC0:1 PA7 5 PB0 6 PB1 7 AREF PB2 8 ADC DAC PB3 9 AC0:1 PB4 ...
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Overview The Atmel bit microcontrollers based on the AVR in a single clock cycle, the AVR achieves throughputs CPU approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption ver- sus processing ...
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The XMEGA devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 Block Diagram Figure 3-1. XMEGA A3U Block Diagram Digital function Programming, debug, test ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA • XMEGA Application Notes This device data sheet only contains part specific information with a short description ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct ...
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Program Memory. This enables instructions to be executed in every clock cycle. The program memory is In-System Self-Programmable Flash memory. 6.3 ALU - Arithmetic Logic Unit The Arithmetic Logic Unit (ALU) supports arithmetic and logic ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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Flash Program Memory The Atmel ory for program storage. The Flash memory can be accessed for read and write both from an external programmer through the PDI, or from application software running in the device. All AVR instructions are ...
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... Byte Address ATxmega128A3U 0 I/O Registers (4K) FFF 1000 EEPROM (2K) 17FF RESERVED 2000 Internal SRAM (8K) 3FFF XMEGA A3U Byte Address ATxmega64A3U 0 I/O Registers (4K) FFF 1000 EEPROM (2K) 17FF RESERVED 2000 Internal SRAM (4K) 2FFF Byte Address ATxmega256A3U 0 I/O Registers (4K) FFF 1000 EEPROM (4K) 1FFF 2000 Internal SRAM (16K) 5FFF 11 ...
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I/O Memory The Status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which is used to transfer ...
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... Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 8386A–AVR–07/11 Table 7-1 on page Device ID bytes for XMEGA A3U devices. Device Byte 2 ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3U XMEGA A3U 13. The serial number consist of the production Device ID bytes Byte ...
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... Table 7-3. Devices EEPROM Size ATxmega64A3U 2K ATxmega128A3U 2K ATxmega192A3U 2K ATxmega256A3U 4K 8386A–AVR–07/11 shows the Flash Program Memory organization. Flash write and erase Number of words and Pages in the Flash. FWORD FPAGE (words) 128 Z[7:1] Z[16:8] ...
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DMAC - Direct Memory Access Controller 8.1 Features • The DMA Controller allows data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – ...
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Event System 9.1 Features • System for direct peripheral to peripheral communication and signaling • Peripherals can directly send, receive and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short ...
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Figure 9-1. The Event Routing Network consists of eight software configurable multiplexers that control how events are routed and used. This is called Event Channels and it enables up to eight parallel event configurations and routings. The maximum routing latency ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32MHz run-time calibrated and tuneable oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz Ultra Low ...
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Figure 10-1. The Clock system, clock sources and clock distribution 10.3 Clock Options 10.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz Ultra Low Power (ULP) Internal Oscillator is a very low power ...
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Crystal Oscillator A 32.768kHz crystal oscillator can be connected between TOSC1 and TOSC2 pins and enable a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can ...
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Power Management and Sleep Modes 11.1 Features • Power management for adjusting power consumption and enabled functions • 5 sleep modes: – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction register to disable clock ...
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Standby Mode Standby mode is identical to Power-down with the exception that the enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time. 11.3.5 Extended Standby Mode Extended ...
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System Control and Reset 12.1 Features • Reset the microcontroller and set it to its initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-On Reset – External Reset – Watchdog ...
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Brown-Out Reset The device is reset when the supply voltage VCC is below the Brown-Out Reset threshold volt- age and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable. 12.3.5 JTAG reset The device is reset as ...
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WDT - Watchdog Timer 13.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronously operation from dedicated oscillator – 1kHz output of the 32kHz Ultra Low Power oscillator • 11 ...
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Interrupts and Programmable Multi-level Interrupt Controller 14.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable Multi-level Interrupt Controller – Interrupt prioritizing according to level and vector address ...
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Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x008 PORTR_INT_base 0x00C DMA_INT_base 0x014 RTC_INT_base 0x018 TWIC_INT_base 0x01C TCC0_INT_base 0x028 TCC1_INT_base 0x030 SPIC_INT_vect 0x032 USARTC0_INT_base 0x03D USARTC1_INT_base 0x03E AES_INT_vect 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base ...
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I/O Ports 15.1 Features • General purpose input and output pins with several and individual configuration options • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O • Input ...
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Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole ...
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Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - ...
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Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Input sensing system overview INVERTED I/O When a pin is configured with inverted I/O, the ...
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T/C - 16-bit Timer/Counter 16.1 Features • Seven 16-bit Timer/Counters – Four Timer/Counters of type 0 – Three Timer/Counters of type 1 • 32-bit Timer/Counter support by cascading two Timer/Counters • Compare or Capture (CC) Channels ...
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A Timer/Counter can be clocked and timed from the Peripheral Clock with optional prescaling or the Event System. The Event System can also be used for direction control, capture trigger or to synchronize operations. Figure 16-1. Overview of a Timer/Counter ...
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AWeX - Advanced Waveform Extension 17.1 Features • Wafeform output with complementary output from each Compare channel • 4 Dead-Time Insertion (DTI) Units – 8-bit Resolution – Separate High and Low Side Dead-Time Setting – Double Buffered Dead-Time – ...
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Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution times (3-bit) • Supports Frequency, Single Slope PWM and Dual Slope PWM generation • Supports the AWEX when this is used for the ...
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RTC - 16-bit Real-Time Counter 19.1 Features • 16-bit resolution • Selectable clock source – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator • Programmable 10-bit clock prescaling • One Compare register ...
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USB - Universal Serial Bus Interface 20.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility ...
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DMA Controller can then read/write one data buffer while the USB module writes/reads the other, and vice versa. This gives double buffered communication. Multi-packet transfer enables a data payload exceeding the maximum packet size of an end- pointto be transferred ...
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TWI - Two Wire Interface 21.1 Features • Two Identical Two Wire Interface peripherals • Bi-directional two-wire communication interface – Phillips I – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – ...
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SPI - Serial Peripheral Interface 22.1 Features • Three Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • Interrupt Flag ...
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USART 23.1 Features • Seven Identical USART peripherals • Full Duplex Operation • Asynchronous or Synchronous Operation – Synchronous clock rates up to 1/2 o the device clock frequency – Asynchronous clock rates up to 1/8 of the device ...
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IRCOM - IR Communication Module 24.1 Features • Pulse modulation/demodulation for infrared communication • IrDA Compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed pulse period, 8-bit programmable ...
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AES and DES Crypto Engine 25.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per ...
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CRC - Cyclic Redundancy Check Generator 26.1 Features • Cyclic Redundancy Check (CRC) Generation and Checking for – Communication Data – Program or Data in Flash memory – Data in SRAM memory and I/O memory space • Integrated with ...
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ADC - 12-bit Analog to Digital Converter 27.1 Features • Two Analog to Digital Converters • 12-bit resolution • Million Samples Per Second – 4 inputs can be sampled within 1.5µs – Down to 2.5µs conversion ...
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The ADC has a compare function for accurate monitoring of user defined thresholds with mini- mum software intervention required. Figure 27-1. ADC overview Internal ADC0 signals • • • ADC15 ADC4 ½x - 64x • • • ADC7 Int. signals ...
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DAC - 12-bit Digital to Analog Converter 28.1 Features • One Digital to Analog Converter (DAC) • 12-bit resolution • 1Million Samples Per Second conversion rate per DAC channel • Built in calibration that removes – Offset ...
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AC - Analog Comparator 29.1 Features • Four Analog Comparators • Selectable propagation delay vs current consumption • Selectable hysteresis – No – Small – Large • Analog Comparator output available on pin • Flexible Input Selection – All ...
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Figure 29-1. Analog comparator overview Pin Input Pin Input DAC Voltage Scaler Bandgap Pin Input Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 29-2. ...
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Programming and Debugging 30.1 Features • Programming – External programming through the PDI or JTAG interface – Bootloader support for programming through any communication interface • Debugging – Non-Intrusive Real-Time On-Chip Debug System – No software or hardware resources ...
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Pinout and Pin Functions The device pinout is shown in I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions ...
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Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK D- D+ 31.1.6 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT RTCOUT 31.1.7 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8386A–AVR–07/11 Serial ...
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Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...
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Table 31-3. Port C - Alternate functions PORT C PIN # INTERRUPT TCC0 PC0 16 SYNC OC0A PC1 17 SYNC OC0B PC2 18 SYNC/ASYNC OC0C PC3 19 SYNC OC0D PC4 20 SYNC PC5 21 SYNC PC6 22 SYNC PC7 23 ...
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Table 31-6. Port F - Alternate functions PORT F PIN # INTERRUPT PF0 46 SYNC PF1 47 SYNC PF2 48 SYNC/ASYNC PF3 49 SYNC PF4 50 SYNC PF5 51 SYNC GND 52 VCC 53 PF6 54 SYNC PF7 53 SYNC ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A3U. For complete register description and summary for each peripheral module, refer to the XMEGA AU Manual. Base Address 0x0000 0x0010 ...
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Base Address 0x0B90 0x0BA0 0x0BC0 8386A–AVR–07/11 Name Description HIRESF High Resolution Extension on port F USARTF0 USART 0 on port F SPIF Serial Peripheral Interface on port F XMEGA A3U 57 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description LAT Z, Rd Load and Toggle RAM location LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd ...
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Packaging information 34.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
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D Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...
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Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 35.1 Absolute Maximum Ratings* ...
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Table 35-1. Current Consumption for Active and sleep modes (Continued) Symbol Parameter Power-save power (2) consumption I CC Reset power consumption Module and peripheral power consumption ULP oscillator 32.768kHz int. oscillator 2MHz int. oscillator 32MHz int. oscillator PLL Real Time ...
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All parameters measured as the difference in current consumption between module enabled and disabled. All data 3.0V, Clk = 1MHz External clock without prescaling 25°C unless other conditiond are given . CC SYS 35.3 ...
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Wakeup time from sleep Table 35-3. Device wakeup time from sleep modes with various system clock sources Symbol Parameter Wake-up time from Idle Wake-up time from Standby Wake-up time from Extend t wakeup Standby Wake-up time from Power-save Wake-up ...
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I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 35-4. I/O Pin Characteristics Symbol Parameter V High ...
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ADC Characteristics Table 35-5. ADC Characteristics Symbol Parameter RES Resolution Conversion time (latency) Sampling Time Clk ADC Clock frequency ADC f Sample rate ADC AVCC Analog supply voltage VREF Reference voltage Rin Input resistance Cin Input capacitance R Reference ...
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Table 35-5. ADC Characteristics (Continued) Symbol Parameter Gain Error Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain ...
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DAC Characteristics Table 35-7. DAC Characteristics Symbol Parameter RES Input Resolution AVREF External reference voltage R DC output impedance channel Linear output voltage range R Reference input resistance AREF C Reference input capacitance AREF Minimum Resistance load Maximum capacitance ...
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Analog Comparator Characteristics Table 35-8. Analog Comparator Characteristics Symbol Parameter V Input Offset Voltage off I Input Leakage Current lk Input voltage range AC startup time V Hysteresis, None hys1 V Hysteresis, Small hys2 V Hysteresis, Large hys3 t ...
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Brownout Detection Characteristics Table 35-10. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...
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Flash and EEPROM Memory Characteristics Table 35-13. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 35-14. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not ...
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Calibrated 2MHz RC Internal Oscillator characteristics Table 35-16. Calibrated 2MHz Internal Oscillator characteristics Symbol Parameter Frequency range Factory calibration accuracy User calibration accuracy DFLL calibration stepsize 35.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics Table 35-17. Calibrated 32MHz Internal ...
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External 32.768kHz Crystal Oscillator and TOSC characteristics Table 35-20. External 32.768kHz Crystal Oscillator and TOSC characteristics Symbol Parameter Recommended crystal equivalent ESR/R1 series resistance (ESR) C Input capacitance between TOSC pins IN_TOSC Recommended Safety factor Note: 1. See Figure ...
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Table 35-21. External Clock used as System Clock without prescaling Symbol Parameter (1) 1/t Clock Frequency CK t Clock Period CK t Clock High Time CH t Clock Low Time CL t Rise Time (for maximum frequency Fall ...
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SPI Characteristics Figure 35-4. SPI Interface Requirements in Master mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) Figure 35-5. SPI Timing Requirements in Slave mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) 8386A–AVR–07/11 ...
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Table 35-23. SPI Timing Characteristics and Requirements Symbol Parameter t SCK Period SCK t SCK high/low width SCKW t SCK Rise time SCKR t SCK Fall time SCKF t MISO setup to SCK MIS t MISO hold after SCK MIH ...
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Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 35-6. Two-Wire Interface Bus ...
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Table 35-24. Two Wire Serial Bus Characteristics (Continued) Symbol Parameter t Data hold time HD;DAT t Data setup time SU;DAT t Setup time for STOP condition SU;STO Bus free time between a STOP and START t BUF condition Notes: 1. ...
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Typical Characteristics 36.1 Active Supply Current Figure 36-1. Active Supply Current vs. Frequency Figure 36-2. Active Supply Current vs. Frequency 8386A–AVR–07/ 1.0MHz External clock 25°C SYS 800 700 600 500 400 300 200 ...
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Figure 36-3. Active Supply Current vs. Vcc Figure 36-4. Active Supply Current vs. Vcc 8386A–AVR–07/ 1.0MHz External Clock SYS 1000 900 800 700 600 500 400 300 200 1.6 1.8 2 2.2 2 2.0MHz internal Oscillator ...
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Idle Supply Current Figure 36-5. Idle Supply Current vs. Frequency Figure 36-6. Idle Supply Current vs. Frequency 8386A–AVR–07/ 1.0MHz 25°C SYS 180 160 140 120 100 0.1 ...
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Figure 36-7. Idle Supply Current vs. Vcc Figure 36-8. Idle Supply Current vs. Vcc 8386A–AVR–07/ 32.768kHz internal Oscillator SYS 1.6 1.8 2 2.2 2 2.0MHz internal Oscillator SYS ...
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Figure 36-9. Idle Supply Current vs. Vcc 36.3 Power-down Supply Current Figure 36-10. Power-down Supply Current vs. Vcc 8386A–AVR–07/ 32MHz internal Oscillator SYS 6.7 6.4 6.1 5.8 5.5 5.2 4.9 4.6 4.3 4.0 2.7 2.8 2.9 3 All ...
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Figure 36-11. Power-down Supply Current vs. Vcc 36.4 Pin Pull-up Figure 36-12. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage 8386A–AVR–07/11 Sampled BOD, WDT, RTC from ULP 3.5 3.2 2.9 2.6 2.3 2 1.7 1.4 1.1 1.6 1.8 ...
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Figure 36-13. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage Figure 36-14. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage 8386A–AVR–07/ 3.0V CC 130 117 104 ...
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Pin Output Voltage vs. Sink/Source Current Figure 36-15. I/O Pin Output Voltage vs. Source Current Figure 36-16. I/O Pin Output Voltage vs. Source Current 8386A–AVR–07/11 Vcc = 1.8V 0 0.2 0.4 0 ...
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Figure 36-17. I/O Pin Output Voltage vs. Source Current Figure 36-18. I/O Pin Output Voltage vs. Source Current 8386A–AVR–07/11 Vcc = 3.3V 1.8 1.95 2.1 2.25 2 -10 -12 -14 -16 -18 - ...
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Figure 36-19. I/O Pin Output Voltage vs. Sink Current Figure 36-20. I/O Pin Sink Current vs. Output Voltage 8386A–AVR–07/11 Vcc = 1.8V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 Vcc = 1.8V ...
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Figure 36-21. I/O Pin Sink Current vs. Output Voltage Figure 36-22. I/O Pin Sink Current vs. Output Voltage 8386A–AVR–07/11 Vcc = 3. 0.05 0.1 0.15 0.2 Vcc = ...
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Pin Thresholds and Hysteresis Figure 36-23. I/O Pin Input Threshold Voltage vs. V Figure 36-24. I/O Pin Input Hysteresis vs. V 8386A–AVR–07/ 25°C 1.85 1.7 1.55 1.4 1.25 1.1 0.95 0.8 0.65 0.5 1.6 1.8 2 2.2 ...
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Figure 36-25. Reset Input Threshold Voltage vs. V Figure 36-26. Reset Input Threshold Voltage vs. V 8386A–AVR–07/ I/O Pin Read as “1” IH 1.65 1.5 1.35 1.2 1.05 0.9 0.75 0.6 0.45 1.6 1.8 2 2.2 2.4 V ...
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Bod Characteristics Figure 36-27. BOD Thresholds vs. Temperature Figure 36-28. BOD Thresholds vs. Temperature 8386A–AVR–07/11 BOD Level = 1.6V 1.632 1.63 1.628 1.626 1.624 1.622 1.62 -45 -35 -25 - BOD Level = 2.6V 2.665 2.66 2.655 ...
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Oscillators 36.8.1 Internal 1kHz Oscillator Figure 36-29. 1kHz Ouput from Internal ULP Oscillator Frequency vs. Temperature 36.8.2 32.768kHz Internal Oscillator Figure 36-30. 32.768kHz Internal Oscillator Frequency vs. Temperature 8386A–AVR–07/11 1.17 1.16 1.15 1.14 1.13 1.12 1.11 1.1 1.09 25 ...
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Internal Oscillator Figure 36-31. 2MHz Internal Oscillator CALA Calibration Step Size Figure 36-32. 2MHz Internal Oscillator Frequency vs. Temperature 8386A–AVR–07/ 0.32 % 0.29 % 0.26 % 0.23 % 0.20 % 0.17 % 0.14 % ...
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Figure 36-33. 2MHz Internal Oscillator Frequency vs. Temperature 36.8.4 32MHZ Internal Oscillator Figure 36-34. Internal 32MHz Oscillator Frequency vs. Temperature 8386A–AVR–07/11 DFLL enabled, from 32.768kHz internal oscillator 2.008 2.005 2.002 1.999 1.996 1.993 1.99 1.987 1.984 1.981 1.978 1.975 -45 ...
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Figure 36-35. 32MHz Internal Oscillator Frequency vs. Temperature Figure 36-36. 32MHz Internal Oscillator CALA Calibration Step Size 8386A–AVR–07/11 DFLL enabled, from 32.768kHz internal oscillator 32.1 32.05 32 31.95 31.9 31.85 31.8 31.75 31.7 31.65 31.6 -45 -35 -25 -15 -5 ...
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Internal Oscillator Calibrated to 48MHZ Figure 36-37. 48MHz Internal Oscillator Frequency vs. Temperature Figure 36-38. 48MHz Internal Oscillator Frequency vs. Temperature 8386A–AVR–07/11 DFLL disabled -45 -35 -25 -15 -5 ...
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Analog comparator characteristics Figure 36-39. AC propagation delay vs. Vcc Figure 36-40. AC propagation delay vs. Temperature 8386A–AVR–07/11 High-speed mode 120 110 100 1.6 1.8 2 2.2 2.4 High-speed mode 120 110 100 ...
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Figure 36-41. AC current consumption vs. Vcc Figure 36-42. AC propagation delay vs. Temperature 8386A–AVR–07/11 Low-power Mode mode 205 200 195 190 185 180 175 170 165 160 155 150 145 1.6 1.8 2 2.2 2.4 Low-spower mode 205 200 ...
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ADC Characteristics Figure 36-43. Gain Error vs. External VREF Figure 36-44. Gain Error vs. V 8386A–AVR–07/11 Differential Mode 3.6V, External reference CC 1 1.2 1.4 1.6 1 ...
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Figure 36-45. Offset vs. External VREF Figure 36-46. Offset vs. V 8386A–AVR–07/11 Differential Mode 3.6V, External reference CC 1 1.2 1.4 1.6 1.8 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 -1.1 CC Differential Mode, ...
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Figure 36-47. Gain Error vs. Temperature Figure 36-48. INL vs. External VREF 8386A–AVR–07/11 Differential Mode 3.6V, External reference CC -45 -35 -25 - -10 -11 ...
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Figure 36-49. DNL vs. External VREF 36.11 DAC characteristics Figure 36-50. DNL vs. External VREF 8386A–AVR–07/11 Differential Mode 3.6V CC 0.87 0.82 0.77 0.72 0.67 0.62 0.57 0.52 0.47 0.42 0.37 1 1.2 1.4 1.6 1 ...
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Figure 36-51. INL vs. External VREF 36.12 PDI characteristics Figure 36-52. Maximum PDI speed vs. Vcc 8386A–AVR–07/ 3.6V, External reference CC 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1 1.2 1.4 1.6 1.8 ...
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Reset pin Pulsewidth Figure 36-53. Minimum Reset Pulse Width vs. Vcc 8386A–AVR–07/11 147 142 137 132 127 122 117 112 107 102 97 92 1.6 1.8 2 2.2 2.4 XMEGA A3U 2.6 2.8 3 3.2 3.4 V [V] CC ...
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... Errata 37.1 ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U 37.1.1 Rev. G • AWeX fault protection restore is not done correct in Pattern Generation Mode 1. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 38.1 8386A – 07/11 1. 8386A–AVR–07/11 Initial revision. XMEGA ...
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Table of Contents Features ..................................................................................................... 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 4 Resources ................................................................................................. 6 5 Capacitive touch sensing ........................................................................ 6 6 AVR CPU ................................................................................................... 7 7 Memories .................................................................................................. 9 8 ...
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Power Management and Sleep Modes ................................................. 21 12 System Control and Reset .................................................................... 23 13 WDT - Watchdog Timer ......................................................................... 25 14 Interrupts and Programmable Multi-level Interrupt Controller .......... 26 15 I/O Ports .................................................................................................. 28 16 T/C - 16-bit ...
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USB - Universal Serial Bus Interface ................................................... 37 21 TWI - Two Wire Interface ....................................................................... 39 22 SPI - Serial Peripheral Interface ............................................................ 40 23 USART ..................................................................................................... 41 24 IRCOM - IR Communication Module .................................................... 42 25 AES and ...
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Pinout and Pin Functions ...................................................................... 51 32 Peripheral Module Address Map .......................................................... 56 33 Instruction Set Summary ...................................................................... 58 34 Packaging information .......................................................................... 62 35 Electrical Characteristics ...................................................................... 64 36 Typical Characteristics .......................................................................... 82 8386A–AVR–07/11 30.1Features ................................................................................................................50 30.2Overview ...............................................................................................................50 ...
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... Characteristics ...............................................................................................95 36.8Oscillators ..............................................................................................................96 36.9Analog comparator characteristics ......................................................................101 36.10ADC Characteristics ..........................................................................................103 36.11DAC characteristics ...........................................................................................106 36.12PDI characteristics ............................................................................................107 36.13Reset pin Pulsewidth .........................................................................................108 37 Errata ..................................................................................................... 109 37.1ATxmega64A3U, ATxmega128A3U, ATxmega192A3U, ATxmega256A3U .......109 38 Datasheet Revision History ................................................................ 110 38.18386A – 07/11 .....................................................................................................110 Table of Contents....................................................................................... i ...
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... Atmel , Atmel logo and combinations thereof, AVR marks of Atmel Corporation or its subsidiaries. Windows other countries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL ...