ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 15

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. DMAC - Direct Memory Access Controller
8.1
8.2
8386A–AVR–07/11
Features
Overview
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The 4-channel Direct Memory Access (DMA) Controller can transfer data between memories
and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates
with minimum CPU intervention, and frees up CPU time. The 4 DMA channels enable up to four
independent and parallel transfers.
The DMA Controller can move data between SRAM and peripherals, between SRAM locations
and between peripheral registers directly. With access to all peripherals the DMA Controller can
handle automatic transfer of data to/from communication modules, as well as data retrieval from
ADC conversions, or data transfer to or from port pins. The DMA Controller can also read from
memory mapped EEPROM.
Data transfers are done in continues bursts of 1, 2, 4 or 8bytes. They build block transfers of
configurable size from 1 to 64Kbytes. A repeat counter can be used to repeat each block trans-
fer for single transactions up to 16Mbytes. Source and destination addressing can be static,
incremental or decremental. Automatic reload of source and/or destination address can be done
after each burst, block transfer, or when transaction is complete. Application software, peripher-
als and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source,
destination, transfer triggers and transaction sizes. They have individual interrupt settings. Inter-
rupt requests can be generated both when a transaction is complete or if the DMA Controller
detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA Controller allows data transfers with minimal CPU intervention
Four DMA Channels with separate
Programmable channel priority
From 1byte to 16Mbytes of data in a single transaction
Multiple addressing modes
Optional reload of source and destination address at the end of each
Optional Interrupt on end of transaction
Optional connection to CRC Generator module for CRC on DMA data
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to peripheral
– transfer triggers
– interrupt vectors
– addressing modes
– Static
– Increment
– Decrement
– Burst
– Block
– Transaction
XMEGA A3U
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