NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 320

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer External Control Register (TEXCON)
TEXCON0
TEXCON1
TEXCON2
TEXCON3
Register
Bits
[31:8]
[7]
[6]
[5]
[4]
TCDB
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
TMR_BA01+0x14 R/W
TMR_BA01+0x34 R/W
TMR_BA23+0x14 R/W
TMR_BA23+0x34 R/W
Offset
Descriptions
Reserved
TCDB
TEXDB
TEXIEN
RSTCAPn
TEXDB
30
22
14
6
TEXIEN
R/W
Reserved
Timer Counter pin De-bounce enable bit
1 = Enable De-bounce
0 = Disable De-bounce
If this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit.
Timer External Capture pin De-bounce enable bit
1 = Enable De-bounce
0 = Disable De-bounce
If this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.
Timer External interrupt Enable Bit
1 = Enable timer External Interrupt
0 = Disable timer External Interrupt
If timer external interrupt is enabled, the timer asserts its external interrupt signal and
sent to NVIC to inform CPU when the transition on the TEX pins associated with
TEX_EDGE(TEXCON[2:1]) setting is happened.
For example, while TEXIEN = 1, TEXEN = 1, and TEX_EDGE = 00, a 1 to 0 transition
on the TEX pin will cause the TEXIF(TEXISR[0]) interrupt flag to be set then the
interrupt signal is generated and sent to NVIC to inform CPU.
Timer External Reset Counter / Capture mode select
29
21
13
5
Timer0 External Control Register
Timer1 External Control Register
Timer2 External Control Register
Timer3 External Control Register
Description
RSTCAPn
28
20
12
4
- 320 -
Reserved
Reserved
Reserved
TEXEN
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
TEX_EDGE
25
17
9
1
Revision V2.01
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
TX_PHASE
24
16
8
0