NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 290

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Example 2, The SPI controller is set as a slave device and connects with an off-chip master
device. The off-chip master device communicates with the on-chip SPI slave controller through
the SPI interface with the following specifications:
The operation flow is as follows.
1)
2) Write the related settings into the SPI_CNTRL register to control this SPI slave actions
4) If this SPI master will transmits (writes) one byte data to the off-chip slave device, write the
5) If this SPI master just only receives (reads) one byte data from the off-chip slave device, you
6) Enable the GO_BUSY bit (SPI_CNTRL [0] = 1) to start the data transfer at the SPI interface.
7) Waiting for SPI interrupt occurred (if the Interrupt Enable IE bit is set) or just polling the
8) Read out the received one byte data from RX0 [7:0] (SPI_RX0[7:0]) register.
9) Go to 4) to continue another data transfer or set SSR [0] to 0 to inactivate the off-chip slave
2.
3.
4.
5.
6.
7.
byte data that will be transmitted into the TX0[7:0] (SPI_TX0[7:0]) register.
don’t need to care what data will be transmitted and just write 0xFF into the SPI_TX0[7:0]
register.
GO_BUSY bit till it is cleared to 0 by hardware automatically.
devices.
Write the SPI_SSR register a proper value for the related settings of slave mode
Select high level and level trigger for the input of slave select signal by setting the Slave
Select Active Level bit SS_LVL (SPI_SSR[2] = 1) and the Slave Select Level Trigger bit
SS_LTRIG (SPI_SSR[4] = 1).
1.
2.
3.
Data bit is latched on positive edge of serial clock
Data bit is driven on negative edge of serial clock
Data is transferred from LSB first
SPICLK is idle at high state
Only one byte of data to be transmitted/received in a transaction
Slave select signal is high level trigger
NuMicro™ NUC130/NUC140 Technical Reference Manual
Force the serial clock idle state at low in CLKP bit (SPI_CNTRL[11] = 0)
Select data transmitted at negative edge of serial clock in TX_NEG bit (SPI_CNTRL[2] =
1)
Select data latched at positive edge of serial clock in RX_NEG bit (SPI_CNTRL[1] = 0)
Set the bit length of word transfer as 8-bit in TX_BIT_LEN bit field (SPI_CNTRL[7:3] =
0x08)
Set only one time of word transfer in TX_NUM (SPI_CNTRL[9:8] = 0x0)
Set MSB transfer first in MSB bit (SPI_CNTRL[10] = 0), and don’t care the SP_CYCLE
bit field (SPI_CNTRL[15:12]) due to it’s not in burst mode in this case
Set this SPI controller as slave device in SLAVE bit (SPI_CNTRL[18] = 1)
Select the serial clock idle state at high in CLKP bit (SPI_CNTRL[11] = 1)
Select data transmitted at negative edge of serial clock in TX_NEG bit (SPI_CNTRL[2] =
1)
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Publication Release Date: June 14, 2011
Revision V2.01