NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 289

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9.6
Example 1, SPI controller is set as a master to access an off-chip slave device with following
specifications:
The operation flow is as follows.
1) Set the DIVIDER (SPI_DIVIDER [15:0]) register to determine the output frequency of serial
2) Write the SPI_SSR register a proper value for the related settings of master mode
3) Write the related settings into the SPI_CNTRL register to control this SPI master actions
SPICLK
SPISS
Programming Examples
MISO
MOSI
clock.
1.
2.
1.
Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=1, CNTRL[TX_NUM]=0x01, CNTRL[TX_BIT_LEN]=0x08
Data bit is latched on positive edge of serial clock
Data bit is driven on negative edge of serial clock
Data is transferred from MSB first
SPICLK is idle at low state
Only one byte of data to be transmitted/received in a transaction
Use the first SPI slave select pin to connect with an off-chip slave device. Slave select signal
is active low
NuMicro™ NUC130/NUC140 Technical Reference Manual
Disable the Automatic Slave Select bit AUTOSS(SPI_SSR[3] = 0)
Select low level trigger output of slave select signal in the Slave Select Active Level bit
SS_LVL (SPI_SSR[2] = 0)
Select slave select signal to be output active at the IO pin by setting the Slave Select
Register bits SSR[0] (SPI_SSR[0]) to active the off-chip slave devices
Set this SPI controller as master device in SLAVE bit (SPI_CNTRL[18] = 0)
SS_LVL=1
SS_LVL=0
CLKP=0
CLKP=1
Figure 5-63 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1 or
2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0
RX0[0]
TX0[0]
LSB
LSB
TX0[1]
RX0[1]
- 289 -
RX0[7]
TX0[7]
Publication Release Date: June 14, 2011
RX1[0]
TX1[0]
RX1[1]
TX1[1]
Revision V2.01
TX1[7]
RX1[7]
MSB
MSB