NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 132

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.8
Power Down Control Register (PWRCON)
Except the BIT[6], all the other bits are protected, program these bits need to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
Register
PWRCON
Bits
[31:9]
[8]
[7]
PWR_DOWN
Register Description
_EN
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
CLK_BA+0x00
Descriptions
Reserved
PD_WAIT_CPU
PWR_DOWN_EN
PD_WU_STS
30
22
14
6
PD_WU_INT_
R/W
R/W
Reserve
This Bit Control the Power Down Entry Condition (write-protection bit)
1 = Chip enter power down mode when the both PD_WAIT_CPU and
0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1
System Power Down Enable Bit (write-protection bit)
When this bit is set to 1, the chip power down mode is enabled and chip power down
behavior will depends on the PD_WAIT_CPU bit
(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately
(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is
When chip wakes up from power down mode, this bit is auto cleared. Users need to set
this bit again for next power down.
When in power down mode, external 4~24 MHz high speed crystal and the internal
22.1184 MHz high speed oscillator will be disabled in this mode, but the external
32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not
controlled by power down mode.
When in power down mode, the PLL and system clock are disabled, and ignored the
clock source selection. The clocks of peripheral are not controlled by power down
EN
29
21
13
5
PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
after the PWR_DOWN_EN bit set.
also active and then the chip enters power down mode
Description
System Power Down Control Register
PD_WU_DLY OSC10K_EN OSC22M_EN XTL32K_EN
Reserved
28
20
12
4
- 132 -
Reserved
Reserved
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
25
17
9
1
Revision V2.01
Reset Value
0x0000_001X
PD_WAIT_CP
XTL12M_EN
24
16
U
8
0