NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 279

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
Slave Select
In master mode, this SPI controller can drive up to two off-chip slave devices through the slave
select output pins SPISSx0 and SPISSx1. In slave mode, the off-chip master device drives the
slave select signal from the SPISSx0 input port to this SPI controller. In master/slave mode, the
active state of slave select signal can be programmed to low active or high active in SS_LVL bit
(SPI_SSR[2]), and the SS_LTRIG bit (SPI_SSR[4]) defines the slave select signal SPISSx0/1 is
level trigger or edge trigger. The selection of trigger condition depends on what type of peripheral
slave/master device is connected.
In slave mode, if the SS_LTRIG bit is configured as level trigger, the LTRIG_FLAG bit
(SPI_SSR[5]) is used to indicate if both the received number and received bits met the
requirement which defines in TX_NUM and TX_BIT_LEN among one transaction done (the
transaction done means the slave select has deactivated or the SPI controller has finished one
data transfer.)
Level-trigger / Edge-trigger
In slave mode, the slave select signal can be configured as level-trigger or edge-trigger. In edge-
trigger, the data transfer starts from an active edge and ends on an inactive edge. If master does
not send an inactive edge to slave, the transfer procedure will not be completed and the interrupt
flag of slave will not be set. In level-trigger, the following two conditions will terminate the transfer
procedure and the interrupt flag of slave will be set. The first condition is that if the number of
transferred bits matches the settings of TX_NUM and TX_BIT_LEN, the interrupt flag of slave will
be set. The second condition, if master set the slave select pin to inactive level during the transfer
is in progress, it will force slave device to terminate the current transfer no matter how many bits
have been transferred and the interrupt flag will be set. User can read the status of LTRIG_FLAG
bit to check if the data has been completely transferred.
Automatic Slave Select
In master mode, if the bit AUTOSS (SPI_SSR[3]) is set, the slave select signals will be generated
automatically and output to SPISSx0 and SPISSx1 pins according to SSR[0] (SPI_SSR[0]) and
SSR[1] (SPI_SSR[1]) whether be enabled or not. It means that the slave select signals, which are
selected in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by
setting the GO_BUSY bit (SPI_CNTRL[0]) and will be de-asserted after the data transfer is
finished. If the AUTOSS bit is cleared, the slave select output signals will be asserted/de-asserted
by manual setting/clearing the related bits of SPI_SSR[1:0]. The active state of the slave select
output signals is specified in SS_LVL bit (SPI_SSR[2]).
Serial Clock
In master mode, set the DIVIDER1 bits (SPI_DIVIDER[15:0]) to program the output frequency of
serial clock to the SPICLK output port. It also supports a variable serial clock if the VARCLK_EN
bit (SPI_CTL[23]) is enabled. In this case, the output frequency of serial clock can be
programmed as one of the two different frequencies which depend on the value of DIVIDER1
(SPI_DIVIDER[15:0]) and DIVIDER2 (SPI_DIVIDER[31:16]). The serial clock rate of each cycle is
depended on the setting of the SPI_VARCLK register.
In slave mode, the off-chip master device drives the serial clock through the SPICLK input port to
this SPI controller.
Publication Release Date: June 14, 2011
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Revision V2.01