PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 6

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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Table of Contents
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.7.2
LPC INTERFACE ...................................................................................................................... 36
2.8.1
2.8.2
2.8.3
REGISTER TYPE ABBREVIATIONS ........................................................................................ 37
SUPERI/O CONFIGURATION REGISTERS ............................................................................. 37
2.10.1
2.10.2
2.10.3
2.10.4
2.10.5
2.10.6
2.10.7
2.10.8
2.10.9
2.10.10 SuperI/O Configuration 9 Register (SIOCF9) .............................................................. 45
2.10.11 SuperI/O Configuration A Register (SIOCFA) ............................................................. 46
FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 47
2.11.1
2.11.2
2.11.3
2.11.4
PARALLEL PORT CONFIGURATION ...................................................................................... 50
2.12.1
2.12.2
2.12.3
SERIAL PORT 2 CONFIGURATION ......................................................................................... 53
2.13.1
2.13.2
2.13.3
SERIAL PORT 1 CONFIGURATION ......................................................................................... 55
2.14.1
2.14.2
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 56
2.15.1
2.15.2
2.15.3
2.15.4
2.15.5
2.15.6
WATCHDOG TIMER (WDT) CONFIGURATION ...................................................................... 61
2.16.1
2.16.2
GPIO Pin Function Lock .............................................................................................. 36
LPC Transactions Supported ...................................................................................... 36
CLKRUN Functionality ................................................................................................. 37
LPCPD Functionality ................................................................................................... 37
SuperI/O ID Register (SID) .......................................................................................... 38
SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 38
SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 39
SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 40
SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 41
SuperI/O Configuration 5 Register (SIOCF5) .............................................................. 42
SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 43
SuperI/O Revision ID Register (SRID) ........................................................................ 43
SuperI/O Configuration 8 Register (SIOCF8) .............................................................. 44
General Description ..................................................................................................... 47
Logical Device 0 (FDC) Configuration ......................................................................... 47
FDC Configuration Register ........................................................................................ 48
Drive ID Register ......................................................................................................... 49
General Description ..................................................................................................... 50
Logical Device 1 (PP) Configuration ............................................................................ 51
Parallel Port Configuration Register ............................................................................ 52
General Description ..................................................................................................... 53
Logical Device 2 (SP2) Configuration .......................................................................... 53
Serial Port 2 Configuration Register ............................................................................ 54
Logical Device 3 (SP1) Configuration .......................................................................... 55
Serial Port 1 Configuration Register ............................................................................ 55
General Description ..................................................................................................... 56
Implementation ............................................................................................................ 56
Logical Device 7 (GPIO) Configuration ....................................................................... 57
GPIO Pin Select Register ............................................................................................ 58
GPIO Pin Configuration Register ................................................................................. 59
GPIO Event Routing Register ...................................................................................... 60
Logical Device 10 (WDT) Configuration ...................................................................... 61
WATCHDOG Timer Configuration Register ................................................................ 61
(Continued)
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