PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 15

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

1.0 Signal/Pin Connection and Description
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY
The signal DC characteristics are denoted by a buffer type symbol, described briefly below and in further detail in Section
9.2. The pin multiplexing information refers to three different types of multiplexing:
1.3 PIN MULTIPLEXING
Table 2 groups all multiplexed PC8739x pins in their associated functional blocks, and provides links to the relevant config-
uration registers and bit values for selecting multiplexed options.
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Functional
Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different
functions. Each function is associated with different board connectivity, and normally, the function selection is deter-
mined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the
BIOS upon power-up, in order to comply with the board implementation.
Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more
modes of operation within the same function. These modes are associated with the same external (board) connectiv-
ity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not
require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O con-
figuration perspective. The mode selection method (registers and bits) as well as the signal specification in each
mode, are described within the functional description of the relevant functional block.
Parallel Port Multiplexer, denoted by a slash (/) between pins in the diagram in Section 1.1. Parallel Port pins can be
used to support external Floppy Disk Controller signals when the PPM is enabled and bit 7 of the SuperI/O Configu-
ration 5 register (SIOCF5) is cleared. See Table 3 for a summary of all PPM options.
Block
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
IN
IN
IN
IN
IN
O
O
OD
PWR
GND
Symbol
PCI
p/n
Signal
C
PCI
STRP
T
TS
n
Input, CMOS compatible
Input, PCI 3.3V
Input, Strap pin with weak pull-down during strap time
Input, TTL compatible
Input, TTL compatible with Schmidt Trigger
Output, PCI 3.3V
Output, push-pull buffer that is capable of sourcing p mA and sinking n mA
Output, open-drain output buffer that is capable of sinking n mA
Power pin
Ground pin
X-Bus
X-Bus
X-Bus
X-Bus
X-Bus
X-Bus
X-Bus
Functional
Block
Table 2. Pin Multiplexing Configuration
XD0
XD1
XD2
XD3
XD4
XD5
XD6
Signal
Table 1. Buffer Types
Game Port
Game Port
Game Port
Game Port
Game Port
Game Port
Game Port
Functional
Block
15
Description
(Continued)
JOYABTN1
JOYBBTN1
JOYAY
JOYBY
JOYBX
JOYAX
JOYBBTN0
Signal
Functional
Block
Signal
2.10.3
2.10.3
2.10.3
2.10.3
2.10.3
2.10.3
2.10.3
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Section
Config