PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 51

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

2.0 Device Architecture and Configuration
2.12.2 Logical Device 1 (PP) Configuration
Table 20 lists the configuration registers which affect the Parallel Port. Only the last register (F0h) is described here. See
Sections 2.2.3 and 2.2.4 for descriptions of the others.
Index
F0h Parallel Port Configuration register
30h Activate. See also bit 0 of the SIOCF1 register.
60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for
61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP
70h Interrupt Number and Wake-Up on IRQ Enable register
71h Interrupt Type
74h DMA Channel Select
75h Report no second DMA assignment
A10) should be 0b.
Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.
Bits 7-2 are read only.
Bit 1 is a read/write bit.
Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation
mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge
interrupt) in all other modes.
Offset
00h
02h
04h
05h
Table 19. Parallel Port Registers at Second Level Offset
Table 20. Parallel Port Configuration Registers
Configuration Register or Action
Mnemonic
PP Confg0
Control0
Control2
Control4
51
(Continued)
Type
R/W
R/W
R/W
R/W
Extended Control 0
Extended Control 1
Extended Control 4
Configuration 0
Register Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Reset
00h
02h
78h
07h
02h
04h
04h
F2h
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